Clock Source Frequency Versus Voltage Scaling; Clock Security System On Hse32 (Css); Table 58. Clock Source Frequency - ST STM32WL5 Series Reference Manual

RM0453
The system clock maximum frequency in range 1 is 48 MHz. After a system reset, the MSI
oscillator, at 4 MHz, is selected as system clock. When a clock source is used directly or
through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is
selected, the switch occurs when the clock source becomes ready. Status bits in the
internal clock sources calibration register (RCC_ICSCR)
ready and which clock is currently used as a system clock.
When waking up from Standby mode, the MSI at 4 MHz is selected as system clock.
In range 2, the system clock must not exceed 16 MHz.
7.2.9

Clock source frequency versus voltage scaling

The following table gives the different clock source frequencies depending on the product
voltage range.
Product voltage
range
Range 1
Range 2
1. The HSEPRE must be set to divide by two.
7.2.10

Clock security system on HSE32 (CSS)

The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE32 oscillator startup delay, and disabled when this oscillator is
stopped.
If a failure is detected on the HSE32 clock, the HSE32 oscillator is automatically disabled. A
clock failure event is sent to the break input of the advanced-control timers (TIM1 and
TIM16/17) and a HSE32 CSS interrupt is generated to inform the software about the failure,
allowing the MCU to perform rescue operations. The HSE32 CSS interrupt is linked to the
CPU1 and CPU2 NMI (non-maskable interrupt) exception vector.
Note: Once the HSE32 CSS is enabled and if the HSE32 clock fails, the HSE32 CSS interrupt
occurs and a NMI is automatically generated. The NMI is executed indefinitely unless the
CSSF pending bit is cleared. As a consequence, in the NMI ISR (interrupt service routine),
the user must clear the HSE CSS interrupt by setting the CSSC bit in the
interrupt clear register
If the HSE32 oscillator is used directly or indirectly as the system clock (indirectly meaning
HSE32 is used as PLL input clock and the PLL clock is used as system clock), a detected
failure causes a switch of the system clock to the MSI or the HSI16 oscillator depending on
the STOPWUCK configuration in the

Table 58. Clock source frequency

MSI HSI16
48 MHz 16 MHz
16 MHz 16 MHz
(RCC_CICR).
RCC clock configuration register
RM0453 Rev 1
Reset and clock control (RCC)
indicate which clock(s) is (are)
Clock frequency
HSE32
PLLRCLK = PLLQCLK = 48 MHz
32 MHz PLLPCLK = 62 MHz
(VCO max = 344 MHz)
PLLRCLK = PLLQCLK = 16 MHz
(1)
32 MHz PLLPCLK = 21 MHz
(VCO max = 128 MHz)
RCC
PLL
RCC clock
(RCC_CFGR), and
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