ST STM32WL5 Series Reference Manual page 304

Reset and clock control (RCC)
Bits 7:4 HPRE[3:0]: HCLK1 prescaler (CPU1, AHB1, and AHB2.)
Caution: Depending on the device voltage range, the software must set correctly these bits to
Bits 3:2 SWS[1:0]: System clock switch status
Bits 1:0 SW[1:0]: System clock switch
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These bits are set and cleared by software to control the division factor of the HCLK1 clock
(CPU1, AHB1, AHB2). The HPREF flag can be checked to know if the programmed HPRE
prescaler value is applied.
0001: SYSCLK divided by 3
0010: SYSCLK divided by 5
0101: SYSCLK divided by 6
0110: SYSCLK divided by 10
0111: SYSCLK divided by 32
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Others: SYSCLK not divided
ensure that the system frequency does not exceed the maximum allowed frequency
(for more details please refer to
management). After a write operation to these bits and before decreasing the
voltage range, the HPREF bit must be read to be sure that the new value has been
taken into account.
These bits are set and cleared by hardware to indicate which clock source is used as system
clock.
00: MSI oscillator used as system clock
01: HSI16 oscillator used as system clock
10: HSE32 used as system clock
11: PLLRCLK used as system clock
These bits are set and cleared by software to select system clock source (SYSCLK). They
are configured by hardware to force MSI oscillator selection when exiting Shutdown mode
and Standby mode.
These bits can also be configured by hardware to force MSI or HSI16 oscillator selection
when exiting Stop mode or in case of failure of the HSE32 oscillator, depending on
STOPWUCK value.
00: MSI selected as system clock
01: HSI16 selected as system clock
10: HSE32 selected as system clock
11: PLLRCLK selected as system clock
Section 6.1.4: Dynamic voltage scaling
RM0453 Rev 1
RM0453