RM0453
CPU1
CPU2
System
mode
0
0
0
0
1
0
0
0
0
1
0
0
Run
0
0
1
1
1
0
0
0
1
0
1
0
1
1
0
(1)
Stop
0
1
1
Standby
1
0
1
N/A
Others
1. Wakeup from Stop 0 and 1 or Stop 2 mode can be detected by the corresponding CnSTOPF and CnSTOP2F.
6.5.5
Sleep mode
I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.
Enter Sleep mode
The Sleep mode is entered from Run mode according to
SLEEPDEEP bit in the CPU system control register is cleared (see
Exit Sleep mode
The MCU exits the Sleep mode (see
Table 48. CPU wakeup versus system operating mode
CPU1 wakeup
0
Wakeup from Run
Wakeup from Stop, but system is
0
already in Run due to CPU2
1
Wakeup from Run
Wakeup from Standby, but system is
0
already in Run due to CPU2
0
Wakeup from Run
Wakeup from Standby followed by Stop,
0
but system is already in Run due to
CPU2
1
Wakeup from Run
1
Wakeup from Stop (CPU2 still in CStop) Wakeup from Stop (CPU1 still in CStop)
Wakeup from Stop after the system has
1
been in Standby (CPU2 still in CStop)
1
Wakeup from Stop (CPU2 still in CStop)
Wakeup from Standby (CPU2 still in
0
CStop)
Not valid, does not occur
Table 49)
as indicated in
RM0453 Rev 1
Power control (PWR)
CPU2 wakeup
Wakeup from Run
Wakeup from Run
Wakeup from Stop, but system is
already in Run due to CPU1
Wakeup from Run
Wakeup from Standby, but system is
already in Run due to CPU1.
Wakeup from Run
Wakeup from Standby followed by Stop,
but system is already in Run due to
CPU1
Wakeup from Stop (CPU1 still in CStop)
Wakeup from Stop after the system
having been in Standby (CPU1 still in
CStop).
Wakeup from Standby (CPU1 still in
CStop)
Enter low-power
mode, when the
Table
49).
Exit low-power
mode.
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