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Power control (PWR)
Bit 4 FPDR: Flash memory power-down mode during LPRun for CPU1
Bit 3 SUBGHZSPINSSSEL: sub-GHz SPI NSS source select
Bits 2:0 LPMS[2:0]: Low-power mode selection for CPU1
Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode must be entered
6.6.2
PWR control register 2 (PWR_CR2)
This register is reset when exiting the Standby mode.
Address offset: 0x004
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 PVME3: Peripheral voltage monitoring 3 enable:
Bits 5:4 Reserved, must be kept at reset value.
256/1461
This bit can only be written to 1 after unlocking this register bit, by first writing (code 0xC1B0)
into this register (when writing the code, the register bits are not updated). Selects whether
the Flash memory is in power-down mode or Idle mode when in LPRun mode. (Flash
memory can only be in power-down mode when code is executed from SRAM). Flash
memory is only set in power-down mode when the system is in LPRun mode, and the
PWR_C2CR1.FPDR bit from CPU2 also allows so.
0: Flash memory in Idle mode when system is in LPRun mode
1: Flash memory in Power-down mode when system is in LPRun mode
This bit is set and cleared by software.
0: sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS
functionality enabled)
1: sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled)
These bits are not reset when exiting Standby mode.
These bits select the low-power mode allowed when CPU1 enters the Deep -Sleep mode.
The system low-power mode entered depends also on the PWR_C2CR1.LPMS[2:0] allowed
low-power mode from CPU2.
000: Stop 0 mode
001: Stop 1 mode
010: Stop 2 mode
011: Standby mode
1xx: Shutdown mode
instead of Stop 2.
In Standby mode, SRAM2 is preserved, depending on RRS bit configuration in
PWR_CR3.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
V
0: PVM3 (
monitoring versus 1.62 V threshold) disable.
DDA
V
1: PVM3 (
monitoring versus 1.62 V threshold) enable.
DDA
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
PVME3
rw
V
DDA
RM0453 Rev 1
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
PLS[2:0]
rw
rw
versus 1.62 V
RM0453
17
16
Res.
Res.
1
0
PVDE
rw
rw
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