ST STM32WL5 Series Reference Manual page 242

Power control (PWR)
mode was entered, as detailed below:
•
If the WFI instruction or return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
•
If the WFE instruction is used to enter the low-power mode, the CPU exits the
low-power mode as soon as an event occurs. The wakeup event can be generated
either by an NVIC IRQ interrupt or by an event.
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–
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From Standby and Shutdown modes, the CPU exits low-power mode through an external
reset (NRST pin), an IWDG reset, a sub-GHz radio IRQ, a PVD event, an edge on the sub-
GHz radio busy signal, a edge on one of the enabled WKUPx pins, an RTC and TAMP
event, or a radio event (for Standby only).
After waking up from Standby or Shutdown mode, the program execution restarts in the
same way as after a reset (boot pin sampling, option bytes loading, reset vector is fetched).
The system mode when it wakes up from low-power mode can be determined from the
CnSTOPF, CnSTOP2F and CnSBF bits in the
register (PWR_EXTSCR).
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Wakeup generated by an NVIC IRQ with SEVONPEND = 0 in the CPU system
control register, enabling an interrupt in the peripheral control register and
in the NVIC)
When the CPU resumes from WFE, the peripheral interrupt pending bit and the
NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending
register) must be cleared. Only NVIC interrupts with sufficient priority wake up and
interrupt the CPU.
Wakeup generated by an NVIC IRQ with SEVONPEND = 1 in the CPU system
control register, enabling an interrupt in the peripheral control register and
optionally in the NVIC
When the CPU resumes from WFE, the peripheral interrupt pending bit and when
enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear
pending register) must be cleared. All NVIC interrupts wake up the CPU, even the
disabled ones. Only enabled NVIC interrupts with sufficient priority wake up and
interrupt the CPU.
Wakeup generated by an event, configuring an EXTI line in event mode
When the CPU resumes from WFE, it is not necessary to clear the EXTI
peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the
pending bits corresponding to the event line is not set. It may be necessary to
clear the interrupt flag in the peripheral.
PWR extended status and status clear
RM0453 Rev 1
RM0453