Pwr Port B Pull-Up Control Register (Pwr_Pucrb); Pwr Port B Pull-Down Control Register (Pwr_Pdcrb) - ST STM32WL5 Series Reference Manual

Power control (PWR)
6.6.11

PWR port B pull-up control register (PWR_PUCRB)

This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x028
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
PU15 PU14 PU13 PU12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PU[15:0]: Port PB[y] pull-up (y = 0 to 15)
When set, each bit activates the pull-up on PB[y] when both APC bits are set in
register 3 (PWR_CR3)
not activated if the corresponding PB[y] bit is also set.
6.6.12

PWR port B pull-down control register (PWR_PDCRB)

This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x02C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
PD15 PD14 PD13 PD12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PD[15:0]: Port PB[y] pull-down (y = 0 to 15)
When set, each bit activates the pull-down on PB[y] when both APC bits are set in
control register 3 (PWR_CR3)
266/1461
28 27 26 25
Res. Res. Res.
12 11 10 9
PU11 PU10 PU9
rw rw rw rw
and in
28 27 26 25
Res. Res. Res.
12 11 10 9
PD11 PD10 PD9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
PU8 PU7 PU6
rw rw rw
PWR CPU2 control register 3
24 23 22
Res. Res. Res.
8 7 6
PD8 PD7 PD6
rw rw rw
and in PWR CPU2 control register 3
RM0453 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PU5 PU4 PU3 PU2
rw rw rw rw
(PWR_C2CR3). The pull-up is
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PD5 PD4 PD3 PD2
rw rw rw rw
(PWR_C2CR3).
RM0453
17 16
Res. Res.
1 0
PU1 PU0
rw rw
PWR control
17 16
Res. Res.
1 0
PD1 PD0
rw rw
PWR