Stop 2 Mode; Table 52. Stop 1 Mode - ST STM32WL5 Series Reference Manual

Power control (PWR)
REGLPS bit can be used to check that the low-power regulator is ready (see the table
below).
Stop 1
Mode entry
Mode exit
Wakeup latency
6.5.9

Stop 2 mode

The Stop 2 mode is based on the CPU Deep-Sleep mode combined with peripheral clock
gating and partial power down of the V
domain are stopped. PLL, MSI, HSI16 and HSE32 oscillators are disabled. Some of the
logic is powered down except for the CPU1, CPU2 and some peripherals with wakeup
capability (I2C3, LPTIM1 and LPUART1), that can switch on the HSI16 to receive a frame,
and switch off HSI16 after receiving the frame if it is not a wakeup frame. In this case, the
HSI16 clock is propagated only to the peripheral requesting it. The Stop 2 mode uses the
low-power regulator, hence the device only enters Stop 2 mode once the low-power
regulator is ready. The REGLPS bit can be used to check that the low-power regulator is
ready.
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Table 52. Stop 1 mode

WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP bit is set in Cortex system control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = 0b001 in PWR_CR1 and/or PWR_C2CR1 or higher
On return from ISR while:
– SLEEPDEEP bit is set in Cortex system control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = 0b001 in PWR_CR1 and/or PWR_C2CR1 or higher
Note: To enter Stop 1 mode, all EXTI line pending bits (in
(EXTI_PR1), and
flags generating wakeup interrupts must be cleared. Otherwise, the Stop 1
mode entry procedure is ignored and program execution continues.
If WFI or return from ISR was used for entry
Any EXTI line configured in Interrupt mode (the corresponding EXTI interrupt
vector must be enabled in the NVIC). The interrupt source can be external
interrupts or peripherals with wakeup capability. Refer to
table, and Table 90: CPU2 vector
If WFE was used for entry and SEVONPEND = 0:
Any EXTI line configured in event mode. Refer to
configurable event input
If WFE was used for entry and SEVONPEND = 1:
Any EXTI line configured in Interrupt mode (even if the corresponding EXTI
interrupt vector is disabled in the NVIC). The interrupt source can be external
interrupts or peripherals with wakeup capability. Refer to
table, and Table 90: CPU2 vector
Wakeup event: refer to
Longest wakeup time between: MSI or HSI16 wakeup time and regulator wakeup
time from Low-power mode + Flash memory wakeup time from Stop 1 mode.
CORE
RM0453 Rev 1
Description
EXTI pending register (EXTI_PR2)), and the peripheral
table.
wakeup.
table.
Table 93: Wakeup interrupts
domain. In Stop 2 mode, all clocks in the V
RM0453
EXTI pending register
Table 89: CPU1 vector
Section 16.4.1: EXTI
Table 89: CPU1 vector
CORE