Pwr Cpu2 Control Register 1 (Pwr_C2Cr1) - ST STM32WL5 Series Reference Manual

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Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PD3: Port PH[3] pull-down

When set, this bit activates the pull-down on PH[3] when both APC bits are set in

control register 3 (PWR_CR3)

Bits 2:0 Reserved, must be kept at reset value.

PWR CPU2 control register 1 (PWR_C2CR1)

This register is reset after wakeup from Standby mode, except for bits [2:0].

The register reset value (0x0000 0007) selects Shutdown mode.

Address offset: 0x080

Reset value: 0x0000 0007

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 FPDS: Flash memory power-down mode during LPSleep for CPU2

Bit 4 FPDR: Flash memory power-down mode during LPRun for CPU2

This bit selects whether the Flash memory is in power-down mode or Idle mode when both

CPUs are in Sleep mode. Flash memory is only set in power-down mode when the system is

in LPSleep mode and the PWR_CR1.FPDS bit from CPU1 also allows so.

0: Flash memory in Idle mode when system is in LPSleep mode

1: Flash memory in power-down mode when system is in LPSleep mode

This bit can only be written to 1 after unlocking this register bit, by first writing (code 0xC1B0)

into this register (when writing the code register bits are not updated). Selects whether the

Flash memory is in power-down mode or Idle mode when in LPRun mode. (Flash memory

can only be in power-down mode when code is executed from SRAM). Flash memory is only

set in power-down mode when the system is in LPRun mode, and the PWR_CR1.FPDR bit

from CPU1 also allows so.

0: Flash memory in Idle mode when system is in LPRun mode

1: Flash memory in power-down mode when system is in LPRun mode

PWR CPU2 control register 3

RM0453 Rev 1

Power control (PWR)

(PWR_C2CR3).

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