Sub-Ghz Radio Generic Packet Control 1A Register (Subghz_Gpktctl1Ar); Sub-Ghz Radio Generic Whitening Lsb Register (Subghz_Gwhiteinirl) - ST STM32WL5 Series Reference Manual

Sub-GHz radio (SUBGHZ)
Bit 7 Reserved, must be kept at reset value.
Bit 6 SBITSYNCEN: LoRa simple bit synchronization enable
Bit 5 RXDINV: LoRa receive data inversion
Bit 4 BITSYNCDIS: LoRa normal bit synchronization enable
Bits 3:0 Reserved, must be kept at reset value.
5.10.2 Sub-GHz radio generic packet control 1A register
(SUBGHZ_GPKTCTL1AR)
Address offset: 0x06B8
Reset value: 0x21
7 6
Res. Res.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 SYNCDETEN: Generic packet synchronization word detection enable
Bit 4 CONTTX: Generic packet continuous transmit enable
Bits 3:2 INFSEQSEL[1:0]: Generic packet infinite sequence selection
Bit 1 INFSQEQEN: Generic packet infinite sequence enable
Bit 0 WHITEINI[8]: Generic packet whitening initial value MSB bit [8]
5.10.3 Sub-GHz radio generic whitening LSB register
(SUBGHZ_GWHITEINIRL)
Address offset: 0x06B9
Reset value: 0x00
7 6
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This bit must be cleared to 0 when using generic packet and BPSK type.
0: simple bit synchronization disabled
1: simple bit synchronization enabled
This bit must be cleared to 0 when using generic packet and BPSK type.
0: receive data not inverted
1: receive data inverted
This bit must be cleared to 0 when using generic packet and BPSK type.
0: normal bit synchronization enabled
1: normal bit synchronization disabled
5
SYNCDETEN CONTTX
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00: preamble 0x5555
01: all zero 0x0000
10: all one 0xFFFF
11: PRBS9
5
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4 3
INFSEQSEL[1:0]
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4 3
WHITEINI[7:0]
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RM0453 Rev 1
2 1
INFSQEQEN
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2 1
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RM0453
0
WHITEINI[8]
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0
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