Flash Cpu2 Access Control Register (Flash_C2Acr); Flash Cpu2 Status Register (Flash_C2Sr) - ST STM32WL5 Series Reference Manual

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Embedded Flash memory (FLASH)

FLASH CPU2 access control register (FLASH_C2ACR)

Address offset: 0x05C

Reset value: 0x0000 0600

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 PES: CPU2 program/erase suspend request

Bits 14:12 Reserved, must be kept at reset value.

Bit 11 ICRST: CPU2 instruction cache reset

Bit 10 Reserved, must be kept at reset value.

Bit 9 ICEN: CPU2 instruction cache enable

Bit 8 PRFTEN: CPU2 prefetch enable.

Bits 7:0 Reserved, must be kept at reset value.

Address offset: 0x060

Reset value: 0x0000 0000

Access: no wait state. Word, half-word and byte access.

0: Flash program and erase operations granted

1: Any new Flash program and erase operation is suspended until this bit and the same bit

in FLASH_ACR are cleared. The PESD bit in FLASH_SR and FLASH_C2SR are set when

at least one PES bit in FLASH_ACR or FLASH_C2ACR is set.

0: CPU2 instruction cache not reset

1: CPU2 instruction cache reset

This bit can be written only when the instruction cache is disabled.

0: CPU2 instruction cache disabled

1: CPU2 instruction cache enabled

0: CPU2 prefetch disabled

1: CPU2 prefetch enabled.

RM0453 Rev 1

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