ST STM32WL5 Series Reference Manual page 147

RM0453
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 RDERRIE: PCROP read error interrupt enable
Bit 25 ERRIE: error interrupt enable
Bit 24 EOPIE: end of operation interrupt enable
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 FSTPG: fast programming
Bit 17 Reserved, must be kept at reset value.
Bit 16 STRT: start
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:3 PNB[6:0]: page number selection
Bit 2 MER: mass erase
27 26 25
Res. ERRIE
rw rw
11 10
Res. Res.
rw
This bit enables the interrupt generation when RDERR in FLASH_SR is set to 1.
0: PCROP read error interrupt disabled
1: PCROP read error interrupt enabled
This bit enables the interrupt generation when OPERR in FLASH_SR is set to 1.
0: OPERR error interrupt disabled
1: OPERR error interrupt enabled
This bit enables the interrupt generation when EOP in FLASH_SR is set to 1.
0: EOP Interrupt disabled
1: EOP Interrupt enabled
0: Fast programming disabled
1: Fast programming enabled
When set, this bit triggers an erase operation. If MER and PER bits are reset and the STRT
bit is set, an unpredictable behavior may occur without generating any error flag. This
condition is forbidden.
This bit is set only by software and is cleared when BSY is cleared in FLASH_SR.
When the system is secure (ESE = 1) starting operations by the CPU1, involving secure
Flash pages is rejected and a bus error is generated.
These bits select the 2-Kbyte page to erase.
0x00: page 0
0x01: page 1
...
0x7F: page 127
This bit triggers the mass erase (all user pages) when set.
24 23 22
EOPIE Res. Res.
rw
9 8 7 6
PNB[6:0]
rw rw rw
RM0453 Rev 1
Embedded Flash memory (FLASH)
21 20 19 18
Res. Res. Res. FSTPG
rw
5 4 3 2
MER
rw rw rw rw
17 16
Res. STRT
rs
1 0
PER PG
rw rw
147/1461
153