Sub-Ghz Radio Power Control Register (Subghz_Pcr); Sub-Ghz Radio Smps Control 2 Register (Subghz_Smpsc2R) - ST STM32WL5 Series Reference Manual

Sub-GHz radio (SUBGHZ)
5.10.27

Sub-GHz radio power control register (SUBGHZ_PCR)

Address offset: 0x091A
Reset value: 0x50
This register is retained in Sleep mode but lost in Deep-Sleep mode.
7 6
Res. CLE
rw
Bit 7 Reserved, must be kept at reset value.
Bit 6 CLE: Power-supply current limiter enable
Bits 5:4 CLV[1:0]: Power-supply current limiter value
Bits 3:0 Reserved, must be kept at reset value.
5.10.28

Sub-GHz radio SMPS control 2 register (SUBGHZ_SMPSC2R)

Address offset: 0x0923
Reset value: 0x06
This register is retained in Sleep mode but lost in Deep-Sleep mode.
7 6
Res Res
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:1 DRV[1:0]: SMPS maximum drive capability.
Bit 0 Reserved, must be kept at reset value.
216/1461
5
CLV[1:0]
rw
0: power-supply current limiter disabled (unlimited current)
1: power-supply current limiter enabled (current limited according to CLV[1:0])
When the power-supply current limiter is enabled by CLEN, these bits define the maximum
current limiting level.
0x0: power-supply current limiting level 25 mA
0x1: power-supply current limiting level 50 mA (default)
0x2: power-supply current limiting level 100 mA
0x3: power-supply current limiting level 200 mA
5
Res
0x0: 20 mA
0x1: 40 mA
0x2: 60 mA
0x3: 100 mA (default)
4 3
Res.
rw
4 3
Res Res
RM0453 Rev 1
2 1
Res. Res.
2 1
DRV[1:0]
rw rw
RM0453
0
Res.
0
Res