ST STM32WL5 Series Reference Manual page 138

Embedded Flash memory (FLASH)
Bit 17 IWDG_STOP: independent watchdog counter freeze in Stop mode
Bit 16 IWDG_SW: independent watchdog selection
Bit 15 Reserved, must be kept at reset value.
Bit 14 nRST_SHDW: reset generation in Shutdown mode
Bit 13 nRST_STDBY: reset generation in Standby mode
Bit 12 nRST_STOP: reset generation in Stop mode
Bits 11:9 BOR_LEV[2:0]: BOR reset Level
Bit 8 ESE: system security enable flag
Bits 7:0 RDP[7:0]: readout protection level
Note: Take care about PCROP_RDP configuration in level 1. Refer to
138/1461
0: Independent watchdog counter frozen in Stop mode
1: Independent watchdog counter running in Stop mode
0: Hardware independent watchdog
1: Software independent watchdog
0: Reset generated when entering the Shutdown mode
1: No reset generated when entering the Shutdown mode
0: Reset generated when entering the Standby mode
1: No reset generated when entering the Standby mode
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode
These bits contain the V
000: BOR level 0. Reset level threshold is around 1.7 V
001: BOR level 1. Reset level threshold is around 2.0 V
010: BOR level 2. Reset level threshold is around 2.2 V
011: BOR level 3. Reset level threshold is around 2.5 V
100: BOR level 4. Reset level threshold is around 2.8 V
When read, this bit indicates whether the system security is enabled, meaning user option
FSD = 0. Writing 0 to this bit and regressing the RDP from level 1 to level 0 disables the
security
0: Security disabled
1: Security enabled
0xAA: Level 0, readout protection not active
0xCC: Level 2, chip readout protection active
Others: Level 1, memories readout protection active
protection for more details.
supply level threshold that activates/releases the reset.
DD
RM0453 Rev 1
RM0453
Level 1: readout