Sub-Ghz Radio Generic Crc Polynomial Lsb Register; Sub-Ghz Radio Generic Synchronization Word Control Register 7; (Subghz_Gsyncr7); Sub-Ghz Radio Generic Synchronization Word Control Register 6 - ST STM32WL5 Series Reference Manual

Sub-GHz radio (SUBGHZ)
5.10.7

Sub-GHz radio generic CRC polynomial LSB register

(SUBGHZ_GCRCPOLRL)
Address offset: 0x06BF
Reset value: 0x21
7 6
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Bits 7:0 CRCPOLI[7:0]: Generic packet CRC initial polynomial LSB bits [7:0]
5.10.8

Sub-GHz radio generic synchronization word control register 7

(SUBGHZ_GSYNCR7)

Address offset: 0x06C0
Reset value: 0x97
7 6
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Bits 7:0 SYNCWORD[63:56]: Eight byte of generic packet synchronization word
5.10.9

Sub-GHz radio generic synchronization word control register 6

(SUBGHZ_GSYNCR6)
Address offset: 0x06C1
Reset value: 0x23
7 6
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Bits 7:0 SYNCWORD[55:48]: Seventh byte of generic packet synchronization word
5.10.10 Sub-GHz radio generic synchronization word control register 5

(SUBGHZ_GSYNCR5)

Address offset: 0x06C2
Reset value: 0x52
7 6
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210/1461
5
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These bits are used for CRC initialization.
5
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5
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5
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4 3
CRCPOLI[7:0]
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4 3
SYNCWORD[63:56]
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4 3
SYNCWORD[55:48]
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4 3
SYNCWORD[47:40]
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RM0453 Rev 1
2 1
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2 1
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2 1
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2 1
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RM0453
0
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0
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0
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0
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