Si/Oi Operation Timing; Clk Polarity Selection - Renesas M16C/6NK Hardware Manual

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M16C/6N Group (M16C/6NK, M16C/6NM)

15.2.1 SI/Oi Operation Timing

Figure 15.39 shows the SI/Oi operation timing.
SI/Oi internal clock
CLKi output
Signal written to the
SiTRR register
SOUTi output
SINi input
IR bit in SiIC register
SiTRF bit in
S3456TRR register
i = 3 to 6 (5 and 6 are only in the 128-pin version.)
* This diagram applies to the case where the bits in the SiC register are set as follows:
SMi2 = 0 (SOUTi output)
SMi3 = 1 (SOUTi output, CLKi function)
SMi4 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
SMi5 = 0 (LSB first)
SMi6 = 1 (internal clock)
NOTES:
1. If the SMi6 bit = 1 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
2. When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
Figure 15.39 SI/Oi Operation Timing

15.2.2 CLK Polarity Selection

The SMi4 bit in the SiC register allows selection of the polarity of the transfer clock.
Figure 15.40 shows the polarity of the transfer clock.
(1) When SMi4 bit in SiC register = 0
CLKi
SOUTi
SINi
(2) When SMi4 bit in SiC register = 1
CLKi
SOUTi
SINi
i = 3 to 6 (5 and 6 are only in the 128-pin version.)
*This diagram applies to the case where the bits in the SiC register are set as follows:
NOTES:
1. When the SMi6 bit = 1 (internal clock), a high level is output from the CLKi pin if not
2. When the SMi6 bit = 1 (internal clock), a low level is output from the CLKi pin if not
Figure 15.40 Polarity of Transfer Clock
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
1.5 cycle (max.) (1)
"H"
"L"
"H"
"L"
"H"
"L"
"H"
D0
"L"
"H"
"L"
"1"
"0"
"1"
"0"
D0 D1
D0 D1
D0 D1
D0 D1
SMi5 = 0 (LSB first)
SMi6 = 1 (internal clock)
transferring data.
transferring data.
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D1 D2 D3 D4
D2 D3 D4 D5 D6
D2 D3 D4 D5 D6
D2 D3 D4 D5 D6
D2 D3 D4 D5 D6
15. Serial Interface
(NOTE 2)
D5 D6 D7
(NOTE 1)
D7
D7
(NOTE 2)
D7
D7