Si/Oi Operation Timing - Renesas M16C/62P Series Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)
17.2.1

SI/Oi Operation Timing

Figure 17.41 shows the SI/Oi Operation Timing.
"H"
SI/Oi internal clock
"L"
"H"
CLKi output
"L"
"H"
Signal written to the
"L"
SiTRR register
SOUTi output
"H"
"L"
"H"
SINi input
"L"
"1"
SiIC register
IR bit "0"
i= 3, 4
NOTES :
1. This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at
the rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
2. When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
3. If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 0.5 to 1.0 transfer clock cycles after writing to the
SiTRR register.
Figure 17.41 SI/Oi Operation Timing
17.2.2 CLK Polarity Selection
The SMi4 bit in the SiC register allows selection of the polarity of the transfer clock. Figure 17.42 shows the
Polarity of Transfer Clock.
(1) When the SMi4 bit in the SiC register = 0
CLKi
SOUTi
SINi
(2) When the SMi4 bit = 1
CLKi
SOUTi
SINi
i=3 and 4
NOTES:
1. This diagram applies to the case where the SiC register bits are set as follows:
2. When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
3. When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
Figure 17.42 Polarity of Transfer Clock
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
(3)
0.5 to 1.0 cycle (max.)
D0
D0 D1 D2
D0 D1 D2
D0 D1 D2
D0 D1 D2
SMi5=0 (LSB first) and SMi6=1 (internal clock)
pin if not transferring data.
pin if not transferring data.
Page 231 of 390
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D1 D2 D3 D4
D3 D4 D5 D6
D3 D4 D5 D6
D3 D4 D5 D6
D3 D4 D5 D6
17. Serial Interface
D5 D6 D7
(NOTE 2)
D7
D7
(NOTE 3)
D7
D7
010-62245566 13810019655
(NOTE 2)