Si/Oi Operation Timing; Clk Polarity Selection - Renesas M16C/62P Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)

17.2.1 SI/Oi Operation Timing

Figure 17.36 shows the SI/Oi operation timing.
"H"
SI/Oi internal clock
"L"
"H"
CLKi output
"L"
Signal written to the
"H"
"L"
SiTRR register
SOUTi output
"H"
"L"
"H"
SINi input
"L"
"1"
SiIC register
IR bit "0"
i= 3, 4
NOTES :
1. This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at
the rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
2. When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
3. If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
Figure 17.36 SI/Oi Operation Timing

17.2.2 CLK Polarity Selection

The SMi4 bit in the SiC register allows selection of the polarity of the transfer clock. Figure 17.37 shows
the polarity of the transfer clock.
(1) When the SMi4 bit in the SiC register = 0
CLKi
SOUTi
SINi
(2) When the SMi4 bit = 1
CLKi
SOUTi
SINi
i=3 and 4
NOTES:
1. This diagram applies to the case where the SiC register bits are set as follows:
SMi5=0 (LSB first) and SMi6=1 (internal clock)
2. When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
pin if not transferring data.
3. When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
pin if not transferring data.
Figure 17.37 Polarity of Transfer Clock
R e . v 2 3 . 0 S e p 0 , 1 2 0 0 4
R E J 0 9 B 0 1 8 5 0 - 2 3 0 Z
1.5 cycle (max.) (3)
D0
D0 D1 D2
D0 D1 D2
D0 D1 D2
D0 D1 D2
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f o 3 6 4
D1 D2 D3
D3 D4 D5 D6
D3 D4 D5 D6
D3 D4 D5 D6
D3 D4 D5 D6
D4 D5 D6 D7
(NOTE 2)
D7
D7
(NOTE 3)
D7
D7
17. Serial I/O
(NOTE 2)