Phase-Delayed Waveform Output Mode - Renesas M16C FAMILY series Hardware Manual

M 1 6 C 2 / 8 G o r u p ( M 1 6 C

13.5.2 Phase-Delayed Waveform Output Mode

Output signal level of the OUTC1j pin is inversed every time the base timer value matches the G1POj
register value ( j=0 to 7). Table 13.9 lists specifications of phase-delayed waveform mode. Figure 13.23
shows an example of phase-delayed waveform mode operation.
Table 13.9 Phase-delayed Waveform Output Mode Specifications
Item
Output waveform
Waveform output start condition
Waveform output stop condition
Interrupt request
(1)
OUTC1j pin
Selectable function
NOTES:
1. The OUTC1 to OUTC1
0
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
• Free-running operation
(the RST1, RST2, and RST4 bits of the G1BCR1 and G1BCR0 registers are set
to "0" (no reset))
Cycle
"H" and "L" width
• The base timer is cleared to "0000
following register
(a) G1PO0 register (enabled by setting RST1 bit to "1", and RST4 and RST2 bits to "0"), or
(b) G1BTRR register (enabled by setting RST4 bit to "1", and RST2 and RST1 bits to "0")
Cycle
"H" and "L" width
n : setting value of either G1PO0 register or G1BTRR register
The IFEj bit in the G1FE register is set to "1" (channel j function enabled)
The IFEj bit is set to "0" (channel j function disabled)
The G1IRj bit in the interrupt request register is set to "1" when the base timer
value matches the G1POj register value. (See Figure 13.23)
Pulse signal output pin
• Default value set function : Set starting waveform output level
• Inverse output function : Waveform output signal is inversed and provided
from the OUTC1j pin
pins.
7
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f o 3 8 5
Specification
65536 x 2
:
f
BT1
65536
:
f
BT1
" by matching the base timer with either
16
2(n+2)
:
f
BT1
n+2
:
f
BT1
13. Timer S