External Interrupts - Renesas H8 Series Hardware Manual

8-bit single-chip microcomputer
Hide thumbs Also See for H8 Series:
Table of Contents

Advertisement

3.3.3

External Interrupts

There are 12 external interrupts: IRQ
Interrupts IRQ
to IRQ
3
IRQ
. These interrupts are detected by either rising edge sensing or falling edge sensing,
0
depending on the settings of bits IEG3 to IEG0 in IEGR1.
When these pins are designated as pins IRQ
edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of
these interrupt requests can be disabled individually by clearing bits IEN3 to IEN0 to 0 in IENR1.
These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ
to IRQ
interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
3
0
numbers 7 to 4 are assigned to interrupts IRQ
to IRQ
(low). Table 3.2 gives details.
3
INT Interrupts: INT interrupts are requested by input signals to pins INT
interrupts are detected by either rising edge sensing or falling edge sensing, depending on the
settings of bits INTEG7 to INTEG0 in IEGR2.
When the designated edge is input at pins INT
requesting an interrupt. Recognition of these interrupt requests can be disabled individually by
clearing bits INTEN7 to INTEN0 to 0 in IENR3. These interrupts can all be masked by setting the
I bit to 1 in CCR.
When INT interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector number 8 is
assigned to the INT interrupts. All eight interrupts have the same vector number, so the interrupt-
handling routine must discriminate the interrupt source.
Note: Pins INT
to INT
7
the designated edge is input or output, the corresponding bit INTFn is set to 1.
to IRQ
3
0
: Interrupts IRQ
to IRQ
0
3
to IRQ
3
3
7
are multiplexed with port 5. Even in port usage of these pins, whenever
0
Section 3 Exception Handling
and INT
to INT
.
7
0
are requested by input signals to pins IRQ
0
in port mode register 1 and the designated
0
to IRQ
. The order of priority is from IRQ
0
to INT
, the corresponding bit in IRR3 is set to 1,
0
Rev. 6.00 Sep 12, 2006 page 71 of 526
to
3
(high)
0
to INT
. These
7
0
REJ09B0326-0600

Advertisement

Table of Contents
loading

Table of Contents