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Renesas H8/3694N Hardware Manual

16-bit single-chip microcomputer

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REJ09B0028-0500

16

Rev.5.00

Revision Date: Nov. 02, 2005

The revision list can be viewed directly by

clicking the title page.

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

Renesas 16-Bit Single-Chip Microcomputer

H8/3694N

H8/3694F

H8/3694

H8/3693

H8/3692

H8/3691

H8/3690

H8/3694

Hardware Manual

H8 Family/H8/300H Tiny Series

HD64N3694G, HD6483694G,

HD64F3694,

HD6433694,

HD6433693,

HD6433692,

HD6433691,

HD6433690,

Group

HD64F3694G,

HD6433694G,

HD6433693G,

HD6433692G,

HD6433691G,

HD6433690G

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Summary of Contents for Renesas H8/3694N

Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3694 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/3694N HD64N3694G, HD6483694G, H8/3694F HD64F3694, HD64F3694G,...
Page 2 Rev.5.00 Nov. 02, 2005 Page ii of xxviii...
Page 3 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 4 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 6 The H8/3694 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU.
Page 7 P87 are input pins, and P86 is an output pin. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8/3694 Group manuals: Document Title Document No.
Page 8 Rev.5.00 Nov. 02, 2005 Page viii of xxviii...
Page 9 Contents Section 1 Overview....................1 Features..........................1 Internal Block Diagram......................4 Pin Arrangement ........................6 Pin Functions ......................... 9 Section 2 CPU......................13 Address Space and Memory Map ..................14 Register Configuration......................17 2.2.1 General Registers....................18 2.2.2 Program Counter (PC) .................... 19 2.2.3 Condition-Code Register (CCR)................
Page 10 3.2.5 Wakeup Interrupt Flag Register (IWPR) ..............55 Reset Exception Handling....................56 Interrupt Exception Handling ....................57 3.4.1 External Interrupts ....................57 3.4.2 Internal Interrupts ....................58 3.4.3 Interrupt Handling Sequence .................. 58 3.4.4 Interrupt Response Time..................60 Usage Notes ......................... 62 3.5.1 Interrupts after Reset....................
Page 11 Mode Transitions and States of LSI..................80 6.2.1 Sleep Mode ......................83 6.2.2 Standby Mode ......................83 6.2.3 Subsleep Mode......................83 6.2.4 Subactive Mode ...................... 84 Operating Frequency in Active Mode.................. 84 Direct Transition ........................85 6.4.1 Direct Transition from Active Mode to Subactive Mode ........85 6.4.2 Direct Transition from Subactive Mode to Active Mode ........
Page 12 9.1.4 Port Pull-Up Control Register 1 (PUCR1)............112 9.1.5 Pin Functions ......................112 Port 2..........................114 9.2.1 Port Control Register 2 (PCR2) ................115 9.2.2 Port Data Register 2 (PDR2) ................115 9.2.3 Pin Functions ......................116 Port 5..........................117 9.3.1 Port Mode Register 5 (PMR5) ................
Page 13 11.3.2 Time Constant Registers A and B (TCORA, TCORB) ........139 11.3.3 Timer Control Register V0 (TCRV0) ..............140 11.3.4 Timer Control/Status Register V (TCSRV) ............142 11.3.5 Timer Control Register V1 (TCRV1) ..............143 11.4 Operation ........................... 144 11.4.1 Timer V Operation....................144 11.5 Timer V Application Examples ..................
Page 14 13.2.1 Timer Control/Status Register WD (TCSRWD) ..........184 13.2.2 Timer Counter WD (TCWD)................185 13.2.3 Timer Mode Register WD (TMWD) ..............186 13.3 Operation ........................... 187 Section 14 Serial Communication Interface 3 (SCI3)........189 14.1 Features..........................189 14.2 Input/Output Pins....................... 191 14.3 Register Descriptions......................
Page 15 Section 15 I C Bus Interface 2 (IIC2) ..............231 15.1 Features..........................231 15.2 Input/Output Pins ....................... 233 15.3 Register Descriptions ......................233 15.3.1 I C Bus Control Register 1 (ICCR1)..............234 15.3.2 I C Bus Control Register 2 (ICCR2)..............236 15.3.3 I C Bus Mode Register (ICMR)................
Page 16 16.5 A/D Conversion Accuracy Definitions ................274 16.6 Usage Notes ........................276 16.6.1 Permissible Signal Source Impedance ..............276 16.6.2 Influences on Absolute Accuracy ................. 276 Section 17 EEPROM..................277 17.1 Features..........................277 17.2 Input/Output Pins....................... 279 17.3 Register Description ......................279 17.3.1 EEPROM Key Register (EKR)................
Page 17 20.2 Register Bits........................307 20.3 Registers States in Each Operating Mode ................311 Section 21 Electrical Characteristics ..............315 21.1 Absolute Maximum Ratings ....................315 21.2 Electrical Characteristics (F-ZTAT™ Version, EEPROM Stacked F-ZTAT Version).......... 315 21.2.1 Power Supply Voltage and Operating Ranges ............315 21.2.2 DC Characteristics ....................
Page 18 Appendix D Package Dimensions ..............405 Appendix E EEPROM Stacked-Structure Cross-Sectional View ..... 410 Main Revisions and Additions in this Edition............. 411 Index ........................415 Rev.5.00 Nov. 02, 2005 Page xviii of xxviii...
Page 19 Section 1 Overview Figure 1.1 Internal Block Diagram of H8/3694 Group of F-ZTAT and Mask-ROM Versions.. 4 Figure 1.2 Internal Block Diagram of H8/3694N (EEPROM Stacked Version) ......5 Figure 1.3 Pin Arrangement of H8/3694 Group of F-ZTAT and Mask-ROM Versions (FP-64E, FP-64A)......................
Page 20 Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators..............69 Figure 5.2 Block Diagram of System Clock Generator ..............70 Figure 5.3 Typical Connection to Crystal Resonator..............70 Figure 5.4 Equivalent Circuit of Crystal Resonator..............70 Figure 5.5 Typical Connection to Ceramic Resonator..............
Page 21 Figure 11.9 Pulse Output Example ..................... 148 Figure 11.10 Example of Pulse Output Synchronized to TRGV Input........149 Figure 11.11 Contention between TCNTV Write and Clear ............150 Figure 11.12 Contention between TCORA Write and Compare Match ........151 Figure 11.13 Internal Clock Switching and TCNTV Operation ..........151 Section 12 Timer W Figure 12.1 Timer W Block Diagram ..................
Page 22 Section 14 Serial Communication Interface 3 (SCI3) Figure 14.1 Block Diagram of SCI3................... 190 Figure 14.2 Data Format in Asynchronous Communication ............205 Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ..... 205 Figure 14.4 Sample SCI3 Initialization Flowchart ..............
Page 23 Figure 15.11 Slave Receive Mode Operation Timing (1)............254 Figure 15.12 Slave Receive Mode Operation Timing (2)............254 Figure 15.13 Clocked Synchronous Serial Transfer Format............255 Figure 15.14 Transmit Mode Operation Timing................. 256 Figure 15.15 Receive Mode Operation Timing ................257 Figure 15.16 Block Diagram of Noise Conceler.................
Page 24 Figure 21.3 Input Timing......................352 Figure 21.4 I C Bus Interface Input/Output Timing ..............352 Figure 21.5 SCK3 Input Clock Timing ..................353 Figure 21.6 SCI Input/Output Timing in Clocked Synchronous Mode ........353 Figure 21.7 EEPROM Bus Timing..................... 354 Figure 21.8 Output Load Circuit ....................
Page 25 Tables Section 1 Overview Table 1.1 Pin Functions ......................9 Section 2 CPU Table 2.1 Operation Notation ....................24 Table 2.2 Data Transfer Instructions..................25 Table 2.3 Arithmetic Operations Instructions (1) ..............26 Table 2.3 Arithmetic Operations Instructions (2) ..............27 Table 2.4 Logic Operations Instructions.................
Page 26 Table 7.5 Additional-Program Data Computation Table ............100 Table 7.6 Programming Time ....................100 Table 7.7 Flash Memory Operating States................105 Section 10 Timer A Table 10.1 Pin Configuration....................132 Section 11 Timer V Table 11.1 Pin Configuration....................138 Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions .......
Page 27 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Table 18.1 LVDCR Settings and Select Functions..............292 Section 21 Electrical Characteristics Table 21.1 Absolute Maximum Ratings ................. 315 Table 21.2 DC Characteristics (1)................... 318 Table 21.2 DC Characteristics (2)................... 322 Table 21.2 DC Characteristics (3)...................
Page 28 Rev.5.00 Nov. 02, 2005 Page xxviii of xxviii...
Page 29 Section 1 Overview Section 1 Overview Features • High-speed H8/300H central processing unit with an internal 16-bit architecture  Upward-compatible with H8/300 CPU on an object level  Sixteen 16-bit general registers  62 basic instructions • Various peripheral functions ...
Page 30 HD6483694G 32 kbytes 1,024 bytes version • General I/O ports  I/O pins: 29 I/O pins (27 I/O pins for H8/3694N), including 8 large current ports (I = 20 mA, @V = 1.5 V)  Input-only pins: 8 input pins (also used for analog input) •...
Page 31 14.0 mm 0.8 mm × LQFP-48 FP-48F 10.0 10.0 mm 0.65 mm × LQFP-48 FP-48B 7.0 mm 0.5 mm × QFN-48 TNP-48 7.0 mm 0.5 mm Only LQFP-64 (FP-64E) for H8/3694N package Rev.5.00 Nov. 02, 2005 Page 3 of 418 REJ09B0028-0500...
Page 32 Section 1 Overview Internal Block Diagram P80/FTCI System P81/FTIOA Subclock clock H8/300H P82/FTIOB generator generator P83/FTIOC P84/FTIOD Data bus (lower) P10/TMOW P14/IRQ0 P15/IRQ1 P74/TMRIV P16/IRQ2 P75/TMCIV P17/IRQ3/TRGV P76/TMOV Timer W SCI3 P50/WKP0 P51/WKP1 P20/SCK3 P52/WKP2 Watchdog P21/RXD Timer A P53/WKP3 timer P22/TXD P54/WKP4...
Page 33 Note: The HD64N3694G is a stacked-structure product in which an EEPROM chip is mounted on the HD64F3694G (F-ZTAT version). The HD6483694G is a stacked-structure product in which an EEPROM chip is mounted on the HD6433694G (mask-ROM version). Figure 1.2 Internal Block Diagram of H8/3694N (EEPROM Stacked Version) Rev.5.00 Nov. 02, 2005 Page 5 of 418 REJ09B0028-0500...
Page 34 Section 1 Overview Pin Arrangement 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P76/TMOV P14/IRQ0 P75/TMCIV P15/IRQ1 P74/TMRIV P16/IRQ2 P57/SCL P17/IRQ3/TRGV P56/SDA PB4/AN4 PB5/AN5 H8/3694 Group PB6/AN6 Top view P10/TMOW PB7/AN7 P55/WKP5/ADTRG PB3/AN3 P54/WKP4 PB2/AN2...
Page 35 Section 1 Overview 36 35 34 33 32 31 30 29 28 27 26 25 P76/TMOV P14/IRQ0 P75/TMCIV P15/IRQ1 P74/TMRIV P16/IRQ2 P57/SCL P17/IRQ3/TRGV P56/SDA PB4/AN4 PB5/AN5 H8/3694 Group PB6/AN6 Top View P10/TMOW PB7/AN7 P55/WKP5/ADTRG PB3/AN3 P54/WKP4 PB2/AN2 P53/WKP3 PB1/AN1 P52/WKP2 PB0/AN0 8 9 10 11 12 Figure 1.4 Pin Arrangement of H8/3694 Group of F-ZTAT...
Page 36 P54/WKP4 PB2/AN2 P53/WKP3 PB1/AN1 P52/WKP2 PB0/AN0 8 9 10 11 12 13 14 15 16 Note: Do not connect NC pins. Figure 1.5 Pin Arrangement of H8/3694N (EEPROM Stacked Version) (FP-64E) Rev.5.00 Nov. 02, 2005 Page 8 of 418 REJ09B0028-0500...
Page 37 Section 1 Overview Pin Functions Table 1.1 Pin Functions Pin No. FP-48F FP-64E FP-48B Type Symbol FP-64A TNP-48 Functions Power Input Power supply pin. Connect this pin to the source system power supply. pins Input Ground pin. Connect this pin to the system power supply (0V).
Page 38 Section 1 Overview Pin No. FP-48F FP-64E FP-48B Type Symbol FP-64A TNP-48 Functions Timer A TMOW Output This is an output pin for divided clocks. Timer V TMOV Output This is an output pin for waveforms generated by the output compare function. TMCIV Input External event input pin.
Page 39 ICE bit in ICCR1 must be set to 1 by using the program. 2. The P57 and P56 pins are not available in the H8/3694N. Rev.5.00 Nov. 02, 2005 Page 11 of 418...
Page 40 Section 1 Overview Rev.5.00 Nov. 02, 2005 Page 12 of 418 REJ09B0028-0500...
Page 41 Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs  Can execute H8/300 CPUs object programs ...
Page 42 Section 2 CPU Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map. HD6433690, HD6433690G HD64F3694, HD64F3694G HD6433691, HD6433691G (Flash memory version) (Mask ROM version) (Mask ROM version) H'0000...
Page 43 Section 2 CPU HD6433692, HD6433692G HD6433693, HD6433693G HD6433694, HD6433694G (Mask ROM version) (Mask ROM version) (Mask ROM version) H'0000 H'0000 H'0000 Interrupt vector Interrupt vector Interrupt vector H'0033 H'0033 H'0033 H'0034 H'0034 H'0034 On-chip ROM (16 kbytes) On-chip ROM (24 kbytes) H'3FFF On-chip ROM (32 kbytes)
Page 44 Section 2 CPU HD64N3694G HD6483694G (On-chip EEPROM module) H'0000 User area (512 bytes) H'01FF Not used H'FF09 Slave address register Not used Figure 2.1 Memory Map (3) Rev.5.00 Nov. 02, 2005 Page 16 of 418 REJ09B0028-0500...
Page 45 Section 2 CPU Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR). General Registers (ERn) (SP) Control Registers (CR)
Page 46 Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers.
Page 47 Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between stack pointer and the stack area. Free area SP (ER7) Stack area...
Page 48 Section 2 CPU Initial Bit Name Value Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. Undefined R/W User Bit Can be written and read by software using the LDC,...
Page 49 Section 2 CPU Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 50 Section 2 CPU Data Type General Data Format Register Word data Word data Longword data [Legend] ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev.5.00 Nov.
Page 51 Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address.
Page 52 Section 2 CPU Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1 Operation Notation Symbol...
Page 53 Section 2 CPU Table 2.2 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd, Cannot be used in this LSI. MOVFPE Rs →...
Page 54 Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register.
Page 55 Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 56 Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 57 Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 58 Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕...
Page 59 Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨...
Page 60 Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access.
Page 61 Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+, R4–1 →...
Page 62 Section 2 CPU (1) Operation field only NOP, RTS, etc. (2) Operation field and register fields ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA(disp) (4) Operation field, effective address extension, and condition field EA(disp) BRA d:8 Figure 2.7 Instruction Formats...
Page 63 Section 2 CPU Table 2.10 Addressing Modes Addressing Mode Symbol Register direct Register indirect @ERn Register indirect with displacement @(d:16,ERn)/@(d:24,ERn) Register indirect with post-increment @ERn+ Register indirect with pre-decrement @–ERn Absolute address @aa:8/@aa:16/@aa:24 Immediate #xx:8/#xx:16/#xx:32 Program-counter relative @(d:8,PC)/@(d:16,PC) Memory indirect @@aa:8 Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the...
Page 64 Section 2 CPU • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register.
Page 65 Section 2 CPU so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions.
Page 66 Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation...
Page 67 Section 2 CPU Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents [Legend] r, rm, rn: Register field Operation field disp: Displacement...
Page 68 Section 2 CPU Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φ ). The period from a rising edge of φ or φ to the next rising edge is called one state. A bus cycle consists of two states or three states.
Page 69 Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 20.1, Register Addresses (Address Order).
Page 70 Section 2 CPU CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11.
Page 71 Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Interrupt Exception- occurs source handling complete Program halt state Program execution state SLEEP instruction executed Figure 2.12 State Transitions Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
Page 72 Section 2 CPU Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B and timer C, not for the group of this LSI.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address.
Page 73 Section 2 CPU • Prior to executing BSET instruction Input/output Input Input Output Output Output Output Output Output Pin state High level level level level level level level level PCR5 PDR5 • BSET instruction executed instruction The BSET instruction is executed for port 5. BSET @PDR5 •...
Page 74 Section 2 CPU • Prior to executing BSET instruction MOV.B #80, The PDR5 value (H'80) is written to a work area in MOV.B R0L, @RAM0 memory (RAM0) as well as to PDR5. MOV.B R0L, @PDR5 Input/output Input Input Output Output Output Output Output...
Page 75 Section 2 CPU an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. • Prior to executing BCLR instruction Input/output Input Input Output Output Output Output Output Output Pin state...
Page 76 Section 2 CPU • Prior to executing BCLR instruction MOV.B #3F, The PCR5 value (H'3F) is written to a work area in MOV.B R0L, @RAM0 memory (RAM0) as well as to PCR5. MOV.B R0L, @PCR5 Input/output Input Input Output Output Output Output Output...
Page 77 Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin.
Page 78 Section 3 Exception Handling Vector Relative Module Exception Sources Number Vector Address Priority Direct transition by executing H'001A to H'001B High the SLEEP instruction External interrupt IRQ0 H'001C to H'001D Low-voltage detection interrupt* IRQ1 H'001E to H'001F IRQ2 H'0020 to H'0021 IRQ3 H'0022 to H'0023 H'0024 to H'0025...
Page 79 Section 3 Exception Handling Register Descriptions Interrupts are controlled by the following registers. • Interrupt edge select register 1 (IEGR1) • Interrupt edge select register 2 (IEGR2) • Interrupt enable register 1 (IENR1) • Interrupt flag register 1 (IRR1) • Wakeup interrupt flag register (IWPR) 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to...
Page 80 Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Initial Bit Name Value Description   7, 6 All 1 Reserved These bits are always read as 1.
Page 81 Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts. Initial Bit Name Value Description IENDT Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled.
Page 82 Section 3 Exception Handling 3.2.4 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3 to IRQ0 interrupt requests. Initial Bit Name Value Description IRRDT Direct Transfer Interrupt Request Flag [Setting condition] When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1.
Page 83 Section 3 Exception Handling Initial Bit Name Value Description IRRl0 IRQ0 Interrupt Request Flag [Setting condition] When IRQ0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI0 is cleared by writing 0 3.2.5 Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Page 84 Section 3 Exception Handling Initial Bit Name Value Description IWPF2 WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF2 is cleared by writing 0. IWPF1 WKP1 Interrupt Request Flag [Setting condition]...
Page 85 Section 3 Exception Handling Interrupt Exception Handling 3.4.1 External Interrupts As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts. NMI Interrupt NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1.
Page 86 Section 3 Exception Handling Reset cleared Initial program instruction prefetch Vector fetch Internal processing φ Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Sequence 3.4.2...
Page 87 Section 3 Exception Handling 2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending. 3. The CPU accepts the NMI and address break without depending on the I bit value. Other interrupt requests are accepted, if the I bit is cleared to 0 in CCR;...
Page 88 Section 3 Exception Handling SP – 4 SP (R7) SP – 3 SP + 1 SP – 2 SP + 2 SP – 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling...
Page 89 Section 3 Exception Handling Figure 3.3 Interrupt Sequence Rev.5.00 Nov. 02, 2005 Page 61 of 418 REJ09B0028-0500...
Page 90 Section 3 Exception Handling Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Page 91 Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Page 92 Section 4 Address Break 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Initial Bit Name Value Description RTINTE RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed.
Page 93 Section 4 Address Break When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used.
Page 94 Section 4 Address Break 4.1.3 Break Address Registers (BARH, BARL) BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF. 4.1.4 Break Data Registers (BDRH, BDRL) BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break...
Page 95 Section 4 Address Break Figures 4.2 show the operation examples of the address break interrupt setting. When the address break is specified in instruction execution cycle Register setting Program • ABRKCR = H'80 0258 • BAR = H'025A 025A 025C MOV.W @H'025A,R0 Underline indicates the address 0260...
Page 96 Section 4 Address Break Rev.5.00 Nov. 02, 2005 Page 68 of 418 REJ09B0028-0500...
Page 97 Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Page 98 Section 5 Clock Pulse Generators System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system clock generator.
Page 99 Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters Frequency (MHz) 500 Ω 120 Ω 80 Ω 60 Ω 50 Ω 40 Ω (max) (max) 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator.
Page 100 Section 5 Clock Pulse Generators Subclock Generator Figure 5.7 shows a block diagram of the subclock generator. 8MΩ Note : Registance is a reference value. Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.8.
Page 101 Section 5 Clock Pulse Generators 5.2.2 Pin Connection when Not Using Subclock When the subclock is not used, connect pin X to V or V and leave pin X open, as shown in figure 5.10. or V Open Figure 5.10 Pin Connection when not Using Subclock Prescalers 5.3.1 Prescaler S...
Page 102 Section 5 Clock Pulse Generators Usage Notes 5.4.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors.
Page 103 Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. •...
Page 104 Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Initial Bit Name Value Description SSBY Software Standby This bit selects the mode to transit after the execution of the SLEEP instruction. 0: a transition is made to sleep mode or subsleep mode.
Page 105 Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 8,192 states 16.4 16,384 states 16.4 32.8 32,768 states 16.4 32.8 65.5 65,536 states 16.4 32.8 65.5...
Page 106 Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Initial Bit Name Value Description SMSEL Sleep Mode Selection LSON Low Speed on Flag DTON Direct Transfer on Flag These bits select the mode to transit after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1.
Page 107 Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Name Value Description   Reserved This bit is always read as 0. MSTIIC IIC Module Standby IIC enters standby mode when this bit is set to 1...
Page 108 Section 6 Power-Down Modes Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction.
Page 109 Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling Transition Mode after SLEEP Instruction Transition Mode due to DTON SSBY SMSEL LSON Execution Interrupt Sleep mode Active mode Subactive mode Subsleep mode Active mode Subactive mode Standby mode Active mode...
Page 110 Section 6 Power-Down Modes Table 6.3 Internal State in Each Operating Mode Subactive Subsleep Standby Function Active Mode Sleep Mode Mode Mode Mode System clock oscillator Functioning Functioning Halted Halted Halted Subclock oscillator Functioning Functioning Functioning Functioning Functioning Instructions Functioning Halted Functioning Halted...
Page 111 Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register.
Page 112 Section 6 Power-Down Modes cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to subactive mode when the bit is 1. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes.
Page 113 Section 6 Power-Down Modes Direct Transition The CPU can execute programs in two modes: active and subactive mode. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in active or subactive mode.
Page 114 Section 6 Power-Down Modes Example Direct transition time = (2 + 1) × 8tw + (8192 + 14) × tosc = 24tw + 8206tosc (when the CPU operating clock of φ /8 → φ and a waiting time of 8192 states are selected) Legend tosc: OSC clock cycle time tw: watch clock cycle time...
Page 115 Section 7 ROM Section 7 ROM The features of the 32-kbyte flash memory built into the flash memory version are summarized below. • Programming/erase methods  The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Page 116 Section 7 ROM H'0000 H'0001 H'0002 Programming unit: 128 bytes H'007F Erase unit H'0080 H'0081 H'0082 H'00FF 1kbyte H'0380 H'0381 H'0382 H'03FF H'0400 H'0401 H'0402 Programming unit: 128 bytes H'047F Erase unit H'0480 H'0481 H'0481 H'04FF 1kbyte H'0780 H'0781 H'0782 H'07FF H'0800 H'0801...
Page 117 Section 7 ROM 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing.
Page 118 Section 7 ROM Initial Bit Name Value Description Program When this bit is set to 1, and while the SWE=1 and PSU=1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled.
Page 119 Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0.
Page 120 Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Page 121 Section 7 ROM On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode.
Page 122 Section 7 ROM pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment.
Page 123 Section 7 ROM Table 7.2 Boot Mode Operation Host Operation Communication Contents LSI Operation Processing Contents Processing Contents Branches to boot program at reset-start. Boot program initiation H'00, H'00 . . . H'00 Continuously transmits data H'00 • Measures low-level period of receive data at specified bit rate.
Page 124 Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 to 20 MHz 9,600 bps 8 to 16 MHz 4,800 bps 4 to 16 MHz 2,400 bps 2 to 16 MHz...
Page 125 Section 7 ROM Reset-start Program/erase? Transfer user program/erase control Branch to flash memory application program to RAM program Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode Rev.5.00 Nov.
Page 126 Section 7 ROM Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode.
Page 127 Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Write pulse application subroutine Apply Write Pulse START Set SWE bit in FLMCR1 WDT enable Wait 1 µs Set PSU bit in FLMCR1 Store 128-byte program data in program Wait 50 µs data area and reprogram data area...
Page 128 Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments Programming completed Reprogram bit — Remains in erased state Table 7.5 Additional-Program Data Computation Table Additional-Program Reprogram Data Verify Data Data Comments Additional-program bit No additional programming No additional programming No additional programming...
Page 129 Section 7 ROM 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed.
Page 130 Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n ← 1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ←...
Page 131 Section 7 ROM Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode.
Page 132 Section 7 ROM entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a reset. Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory.
Page 133 Section 7 ROM Table 7.7 Flash Memory Operating States Flash Memory Operating State LSI Operating State PDWND = 0 (Initial value) PDWND = 1 Active mode Normal operating mode Normal operating mode Subactive mode Power-down mode Normal operating mode Sleep mode Normal operating mode Normal operating mode Subsleep mode...
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Page 135 H'FB80 to H'FF7F H8/3692 512 kbytes H'FD80 to H'FF7F H8/3691 512 kbytes H'FD80 to H'FF7F H8/3690 512 kbytes H'FD80 to H'FF7F EEPROM Flash H8/3694N 2 kbytes H'F780 to H'FF7F* stacked memory version version Mask-ROM 1 kbyte H'FB80 to H'FF7F version Note: When the E7 or E8 is used, area H'F780 to H'FB7F must not be accessed.
Page 136 Section 8 RAM Rev.5.00 Nov. 02, 2005 Page 108 of 418 REJ09B0028-0500...
Page 137 Section 9 I/O Ports The group of this LSI has twenty-nine general I/O ports (twenty-seven general I/O ports in the H8/3694N) and eight general input-only ports. Port 8 is a large current port, which can drive 20 mA (@V = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset.
Page 138 Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Initial Bit Name Value Description IRQ3 P17/IRQ3/TRGV Pin Function Switch This bit selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV.
Page 139 Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Initial Bit Name Value Description PCR17 When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the PCR16 corresponding pin an output port, while clearing the bit to...
Page 140 Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Name Value Description PUCR17 Only bits for which PCR1 is cleared are valid. The pull-up MOS of P17 to P14 and P12 to P10 pins enter the on- PUCR16 state when these bits are set to 1, while they enter the...
Page 141 Section 9 I/O Ports P15/IRQ1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Pin Function Setting value 0 P15 input pin P15 output pin IRQ1 input pin Legend: X: Don't care. P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function Setting value 0 P14 input pin...
Page 142 Section 9 I/O Ports P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Pin Function Setting value 0 P10 input pin P10 output pin TMOW output pin Legend: X: Don't care. Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2.
Page 143 Section 9 I/O Ports 9.2.1 Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Initial Bit Name Value Description    7 to 3 Reserved PCR22 When each of the port 2 pins P22 to P20 functions as an general I/O port, setting a PCR2 bit to 1 makes the...
Page 144 Section 9 I/O Ports 9.2.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P22/TXD pin Register PMR1 PCR2 Bit Name PCR22 Pin Function Setting P22 input pin Value P22 output pin TXD output pin Legend: X: Don't care.
Page 145 C bus interface register has priority for functions of the pins P57/SCL and P56/SDA. Since the output buffer for pins P56 and P57 has the NMOS push-pull structure, it differs from an output buffer with the CMOS structure in the high-level output characteristics (see section 21, Electrical Characteristics). H8/3694 H8/3694N P57/SCL P56/SDA P55/WKP5/ADTRG P55/WKP5/ADTRG...
Page 146 Section 9 I/O Ports 9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Initial Bit Name Value Description   7, 6 All 0 Reserved These bits are always read as 0. WKP5 P55/WKP5/ADTRG Pin Function Switch Selects whether pin P55/WKP5/ADTRG is used as P55 or as WKP5/ADTRG input.
Page 147 PCR56 corresponding pin an output port, while clearing the bit to PCR55 0 makes the pin an input port. PCR54 Note: The PCR57 and PCR56 bits should not be set to 1 in the H8/3694N. PCR53 PCR52 PCR51 PCR50 9.3.3 Port Data Register 5 (PDR5) PDR5 is a general I/O port data register of port 5.
Page 148 Section 9 I/O Ports 9.3.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Name Value Description   7, 6 All 0 Reserved These bits are always read as 0. PUCR55 Only bits for which PCR5 is cleared are valid.
Page 149 Section 9 I/O Ports P56/SDA pin Register ICCR1 PCR5 Bit Name PCR56 Pin Function Setting P56 input pin Value P56 output pin SDA I/O pin Legend: X: Don't care. SDA performs the NMOS open-drain output, that enables a direct bus drive. P55/WKP5/ADTRG pin Register PMR5...
Page 150 Section 9 I/O Ports P53/WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Pin Function Setting P53 input pin Value P53 output pin WKP3 input pin Legend: X: Don't care. P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Pin Function Setting P52 input pin Value...
Page 151 Section 9 I/O Ports P50/WKP0 pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Pin Function Setting P50 input pin Value P50 output pin WKP0 input pin Legend: X: Don't care. Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4.
Page 152 Section 9 I/O Ports 9.4.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Initial Bit Name Value Description    Reserved PCR76 Setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an PCR75 input port.
Page 153 Section 9 I/O Ports 9.4.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P76/TMOV pin Register TCSRV PCR7 Bit Name OS3 to OS0 PCR76 Pin Function Setting 0000 P76 input pin Value P76 output pin Other than TMOV output pin the above...
Page 154 Section 9 I/O Ports Port 8 Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W has priority for functions of the pins P84/FTIOD, P83/FTIOC, P82/FTIOB, and P81/FTIOA.
Page 155 Section 9 I/O Ports 9.5.2 Port Data Register 8 (PDR8) PDR8 is a general I/O port data register of port 8. Initial Bit Name Value Description PDR8 stores output data for port 8 pins. If PDR8 is read while PCR8 bits are set to 1, the value stored in PDR8 is read.
Page 156 Section 9 I/O Ports P85 pin Register PCR8 Bit Name PCR85 Pin Function Setting P85 input pin Value P85 output pin P84/FTIOD pin Register TIOR1 PCR8 Bit Name IOD2 IOD1 IOD0 PCR84 Pin Function Setting P84 input/FTIOD input pin Value P84 output/FTIOD input pin FTIOD output pin FTIOD output pin...
Page 157 Section 9 I/O Ports P82/FTIOB pin Register TIOR0 PCR8 Bit Name IOB2 IOB1 IOB0 PCR82 Pin Function Setting P82 input/FTIOB input pin Value P82 output/FTIOB input pin FTIOB output pin FTIOB output pin P82 input/FTIOB input pin P82 output/FTIOB input pin Legend: X: Don't care.
Page 158 Section 9 I/O Ports Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.6. PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 Port B PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.6 Port B Pin Configuration...
Page 159 Section 10 Timer A Section 10 Timer A Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10.1 shows a block diagram of timer A. 10.1 Features •...
Page 160 Section 10 Timer A φ φ φ φ φ φ /128 φ TMOW φ φ /8192, φ /4096, φ φ /2048, φ /512, φ φ /256, φ /128, φ φ /32, φ /8 φ IRRTA [Legend] TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag...
Page 161 Section 10 Timer A 10.3 Register Descriptions Timer A has the following registers. • Timer mode register A (TMA) • Timer counter A (TCA) 10.3.1 Timer Mode Register A (TMA) TMA selects the operating mode, the divided clock output, and the input clock. Initial Bit Name Value...
Page 162 Section 10 Timer A Initial Bit Name Value Description TMA2 Internal Clock Select 2 to 0 TMA1 These bits select the clock input to TCA when TMA3 = 0. 000: φ/8192 TMA0 001: φ/4096 010: φ/2048 011: φ/512 100: φ/256 101: φ/128 110: φ/32 111: φ/8...
Page 163 Section 10 Timer A 10.4 Operation 10.4.1 Interval Timer Operation When bit TMA3 in TMA is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting of timer A resume immediately as an interval timer.
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Page 165 Section 11 Timer V Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle.
Page 166 Section 11 Timer V TCRV1 TCORB Trigger TRGV control Comparator Clock select TMCIV TCNTV Comparator φ TCORA Clear TCRV0 TMRIV control Interrupt request control Output TMOV TCSRV control CMIA CMIB [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV:...
Page 167 Section 11 Timer V 11.3 Register Descriptions Time V has the following registers. • Timer counter V (TCNTV) • Timer constant register A (TCORA) • Timer constant register B (TCORB) • Timer control register V0 (TCRV0) • Timer control/status register V (TCSRV) •...
Page 168 Section 11 Timer V 11.3.3 Timer Control Register V0 (TCRV0) TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Initial Bit Name Value Description CMIEB Compare Match Interrupt Enable B When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled.
Page 169 Section 11 Timer V Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 TCRV1 Bit 2 Bit 1 Bit 0 Bit 0 CKS2 CKS1 CKS0 ICKS0 Description  Clock input prohibited Internal clock: counts on φ/4, falling edge Internal clock: counts on φ/8, falling edge Internal clock: counts on φ/16, falling edge Internal clock: counts on φ/32, falling edge...
Page 170 Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Initial Bit Name Value Description CMFB Compare Match Flag B Setting condition: When the TCNTV value matches the TCORB value Clearing condition: After reading CMFB = 1, cleared by writing 0 to CMFB CMFA...
Page 171 Section 11 Timer V OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match. 11.3.5 Timer Control Register V1 (TCRV1) TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to...
Page 172 Section 11 Timer V 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up.
Page 173 Section 11 Timer V φ Internal clock TCNTV input clock N – 1 N + 1 TCNTV Figure 11.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock N – 1 N + 1 TCNTV Figure 11.3 Increment Timing with External Clock φ...
Page 174 Section 11 Timer V φ TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output Figure 11.6 TMOV Output Timing φ Compare match A signal H'00 TCNTV Figure 11.7 Clear Timing by Compare Match...
Page 175 Section 11 Timer V φ TMRIV(External counter reset input pin ) TCNTV reset signal N – 1 H'00 TCNTV Figure 11.8 Clear Timing by TMRIV Input Rev.5.00 Nov. 02, 2005 Page 147 of 418 REJ09B0028-0500...
Page 176 Section 11 Timer V 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA.
Page 177 Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1.
Page 178 Section 11 Timer V 11.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out.
Page 179 Section 11 Timer V TCORA write cycle by CPU φ TCORA address Address Internal write signal TCNTV TCORA TCORA write data Compare match signal Inhibited Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV Write to CKS1 and CKS0...
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Page 181 Section 12 Timer W Section 12 Timer W The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers.
Page 182 Section 12 Timer W Table 12.1 Timer W Functions Input/Output Pins Item Counter FTIOA FTIOB FTIOC FTIOD Internal clocks: φ, φ/2, φ/4, φ/8 Count clock External clock: FTCI General registers Period GRC (buffer GRD (buffer (output compare/input specified in register for register for capture registers) GRA in...
Page 183 Section 12 Timer W φ Internal clock: FTIOA φ/2 Clock φ/4 FTIOB selector φ/8 FTIOC Control logic External clock: FTCI FTIOD Comparator IRRTW Internal data bus [Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 bits)
Page 184 Section 12 Timer W 12.2 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.2 Pin Configuration Name Abbreviation Input/Output Function External clock input FTCI Input External clock input pin Input capture/output FTIOA Input/output Output pin for GRA output compare compare A or input pin for GRA input capture Input capture/output...
Page 185 Section 12 Timer W 12.3.1 Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Initial Bit Name Value Description Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1.
Page 186 Section 12 Timer W 12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Initial Bit Name Value Description CCLR Counter Clear The TCNT value is cleared by compare match A when this bit is 1.
Page 187 Section 12 Timer W Initial Bit Name Value Description Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1* Legend: X: Don't care.
Page 188 Section 12 Timer W 12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Initial Bit Name Value Description Timer Overflow Flag [Setting condition] When TCNT overflows from H'FFFF to H'0000 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF ...
Page 189 Section 12 Timer W Initial Bit Name Value Description IMFB Input Capture/Compare Match Flag B [Setting conditions] • TCNT = GRB when GRB functions as an output compare register • The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register [Clearing condition]...
Page 190 Section 12 Timer W Initial Bit Name Value Description IOB1 I/O Control B1 and B0 IOB0 When IOB2 = 0, 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1,...
Page 191 Section 12 Timer W 12.3.6 Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Initial Bit Name Value Description   Reserved This bit is always read as 1. IOD2 I/O Control D2 Selects the GRD function.
Page 192 Section 12 Timer W Initial Bit Name Value Description IOC1 I/O Control C1 and C0 IOC0 When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1,...
Page 193 Section 12 Timer W (IMIEA, IMIEB, IMIEC, or IMIED) in TSRW is set to 1 at this time, an interrupt request is generated. The edge of the input-capture signal is selected in TIOR. GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA and BUFEB in TMRW.
Page 194 Section 12 Timer W TCNT value H'FFFF H'0000 Time CTS bit Flag cleared by software Figure 12.2 Free-Running Counter Operation Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1.
Page 195 Section 12 Timer W TCNT value H'FFFF Time H'0000 No change No change FTIOA FTIOB No change No change Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1) Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B.
Page 196 Section 12 Timer W The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured.
Page 197 Section 12 Timer W TCNT value H'FFFF H'DA91 H'5480 H'0245 H'0000 Time FTIOA H'0245 H'5480 H'DA91 H'0245 H'5480 Figure 12.8 Buffer Operation Example (Input Capture) 12.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers.
Page 198 Section 12 Timer W TCNT value Counter cleared by compare match A H'0000 Time FTIOB FTIOC FTIOD Figure 12.9 PWM Mode Example (1) Figure 12.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0: initial output values are set to 1).
Page 199 Section 12 Timer W Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A.
Page 200 Section 12 Timer W TCNT value Write to GRB Write to GRB H'0000 Time Duty 0% FTIOB Output does not change when cycle register and duty register compare matches occur TCNT value simultaneously. Write to GRB Write to GRB Write to GRB H'0000 Time Duty 100%...
Page 201 Section 12 Timer W TCNT value Write to GRB Write to GRB H'0000 Time Duty 100% FTIOB Output does not change when cycle register and duty register compare matches occur TCNT value simultaneously. Write to GRB Write to GRB Write to GRB H'0000 Time Duty 0%...
Page 202 Section 12 Timer W 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure 12.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles;...
Page 203 Section 12 Timer W Figure 12.16 shows the output compare timing. φ TCNT input clock TCNT GRA to GRD Compare match signal FTIOA to FTIOD Figure 12.16 Output Compare Output Timing 12.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1.
Page 204 Section 12 Timer W 12.5.4 Timing of Counter Clearing by Compare Match Figure 12.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1. φ...
Page 205 Section 12 Timer W φ Input capture signal TCNT GRA, GRB GRC, GRD Figure 12.20 Buffer Operation Timing (Input Capture) 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register.
Page 206 Section 12 Timer W 12.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 12.22 shows the timing of the IMFA to IMFD flag setting at input capture.
Page 207 Section 12 Timer W 12.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. 2.
Page 208 Section 12 Timer W Previous clock New clock Count clock TCNT The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 12.25 Internal Clock Switching and TCNT Operation Rev.5.00 Nov. 02, 2005 Page 180 of 418 REJ09B0028-0500...
Page 209 Section 12 Timer W 5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the values read from the TOA to TOD bits may differ.
Page 210 Section 12 Timer W Rev.5.00 Nov. 02, 2005 Page 182 of 418 REJ09B0028-0500...
Page 211 Section 13 Watchdog Timer Section 13 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 13.1.
Page 212 Section 13 Watchdog Timer 13.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 13.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state.
Page 213 Section 13 Watchdog Timer Initial Bit Name Value Description WDON Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0. [Setting condition] When 1 is written to the WDON bit while writing 0 to the B2WI bit when the TCSRWE bit=1 [Clearing conditions] Reset by RES pin...
Page 214 Section 13 Watchdog Timer 13.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Initial Bit Name Value Description   7 to 4 All 1 Reserved These bits are always read as 1. CKS3 Clock Select 3 to 0 CKS2 Select the clock to be input to TCWD.
Page 215 Section 13 Watchdog Timer 13.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated.
Page 216 Section 13 Watchdog Timer Rev.5.00 Nov. 02, 2005 Page 188 of 418 REJ09B0028-0500...
Page 217 Section 14 Serial Communication Interface 3 (SCI3) Section 14 Serial Communication Interface 3 (SCI3) Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
Page 218 Section 14 Serial Communication Interface 3 (SCI3) Internal clock (φ/64, φ/16, φ/4, φ) External SCK 3 clock Baud rate generator Clock Transmit/receive SCR3 control circuit Interrupt request (TEI, TXI, RXI, ERI) [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR:...
Page 219 Section 14 Serial Communication Interface 3 (SCI3) 14.2 Input/Output Pins Table 14.1 shows the SCI3 pin configuration. Table 14.1 Pin Configuration Pin Name Abbreviation Function SCI3 clock SCK3 SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output...
Page 220 Section 14 Serial Communication Interface 3 (SCI3) 14.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.
Page 221 Section 14 Serial Communication Interface 3 (SCI3) 14.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator clock source. Initial Bit Name Value Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length.
Page 222 Section 14 Serial Communication Interface 3 (SCI3) Initial Bit Name Value Description CKS1 Clock Select 0 and 1 CKS0 These bits select the clock source for the on-chip baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relationship between the bit rate register setting...
Page 223 Section 14 Serial Communication Interface 3 (SCI3) Initial Bit Name Value Description MPIE Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is prohibited.
Page 224 Section 14 Serial Communication Interface 3 (SCI3) 14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Initial Bit Name Value...
Page 225 Section 14 Serial Communication Interface 3 (SCI3) Initial Bit Name Value Description Parity Error [Setting condition] • When a parity error is generated during reception [Clearing condition] • When 0 is written to PER after reading PER = 1 TEND Transmit End [Setting conditions] •...
Page 226 Section 14 Serial Communication Interface 3 (SCI3) 14.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode.
Page 227 Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.00 0.16 0.16 0.21...
Page 228 Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bit/s) –0.44 0.08 –0.07 0.03 0.16 0.00 0.00 0.16 0.16 0.00...
Page 229 Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ (MHz) 14.7456 Bit Rate Error Error Error (bit/s) –0.17 0.70 0.03 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16...
Page 230 Section 14 Serial Communication Interface 3 (SCI3) Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Bit Maximum Bit φ (MHz) φ (MHz) Rate (bit/s) Rate (bit/s) 62500 250000 2.097152 65536 9.8304 307200 2.4576 76800 312500 93750 375000 3.6864 115200 12.288...
Page 231 Section 14 Serial Communication Interface 3 (SCI3) Table 14.4 Examples of BBR Setting for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) — — — — — — — — — — — — 2.5k 100k 250k 500k...
Page 232 Section 14 Serial Communication Interface 3 (SCI3) Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) — — — — — — — — 2.5k 100k 250k 500k — —...
Page 233 Section 14 Serial Communication Interface 3 (SCI3) 14.4 Operation in Asynchronous Mode Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level).
Page 234 Section 14 Serial Communication Interface 3 (SCI3) 14.4.2 SCI3 Initialization Follow the flowchart as shown in figure 14.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR.
Page 235 Section 14 Serial Communication Interface 3 (SCI3) 14.4.3 Data Transmission Figure 14.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 236 Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is Read TDRE flag in SSR written to TDR, the TDRE flag is automaticaly cleared to 0.
Page 237 Section 14 Serial Communication Interface 3 (SCI3) 14.4.4 Serial Data Reception Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
Page 238 Section 14 Serial Communication Interface 3 (SCI3) Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1.
Page 239 Section 14 Serial Communication Interface 3 (SCI3) [1] Read the OER, PER, and FER flags in Start reception SSR to identify the error. If a receive error occurs, performs the appropriate error processing. Read OER, PER, and [2] Read SSR and check that RDRF = 1, FER flags in SSR then read the receive data in RDR.
Page 240 Section 14 Serial Communication Interface 3 (SCI3) Error processing OER = 1 Overrun error processing FER = 1 Break? Framing error processing PER = 1 Parity error processing Clear OER, PER, and FER flags in SSR to 0 <End> Figure 14.8 Sample Serial Reception Data Flowchart (2) Rev.5.00 Nov.
Page 241 Section 14 Serial Communication Interface 3 (SCI3) 14.5 Operation in Clocked Synchronous Mode Figure 14.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Page 242 Section 14 Serial Communication Interface 3 (SCI3) 14.5.3 Serial Data Transmission Figure 14.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 243 Section 14 Serial Communication Interface 3 (SCI3) Serial clock Serial Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 data 1 frame 1 frame TDRE TEND TXI interrupt TDRE flag TXI interrupt request generated TEI interrupt request operation request cleared...
Page 244 Section 14 Serial Communication Interface 3 (SCI3) Start transmission Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag Read TDRE flag in SSR is automatically cleared to 0 and clocks are output to start the data transmission.
Page 245 Section 14 Serial Communication Interface 3 (SCI3) 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data.
Page 246 Section 14 Serial Communication Interface 3 (SCI3) Start reception Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read OER flag in SSR Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR.
Page 247 Section 14 Serial Communication Interface 3 (SCI3) 14.5.5 Simultaneous Serial Data Transmission and Reception Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations.
Page 248 Section 14 Serial Communication Interface 3 (SCI3) Start transmission/reception [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the Read TDRE flag in SSR TDRE flag is automatically cleared to [2] Read SSR and check that the RDRF TDRE = 1...
Page 249 Section 14 Serial Communication Interface 3 (SCI3) 14.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Page 250 Section 14 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle =...
Page 251 Section 14 Serial Communication Interface 3 (SCI3) Start transmission Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in Read TDRE flag in SSR SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
Page 252 Section 14 Serial Communication Interface 3 (SCI3) 14.6.2 Multiprocessor Serial Data Reception Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 253 Section 14 Serial Communication Interface 3 (SCI3) Set the MPIE bit in SCR3 to 1. Start reception Read OER and FER in SSR to check for errors. Receive error processing is performed Set MPIE bit in SCR3 to 1 in cases where a receive error occurs. Read SSR and check that the RDRF flag is Read OER and FER flags in SSR set to 1, then read the receive data in RDR...
Page 254 Section 14 Serial Communication Interface 3 (SCI3) Error processing OER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear OER, and FER flags in SSR to 0 <End> Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev.5.00 Nov.
Page 255 Section 14 Serial Communication Interface 3 (SCI3) Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI interrupt RDRF flag RXI interrupt request operation request cleared is not generated, and MPIE cleared to 0...
Page 256 Section 14 Serial Communication Interface 3 (SCI3) 14.7 Interrupts The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6 shows the interrupt sources. Table 14.6 SCI3 Interrupt Requests Interrupt Requests Abbreviation...
Page 257 Section 14 Serial Communication Interface 3 (SCI3) 14.8 Usage Notes 14.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0, setting the FER flag, and possibly the PER flag.
Page 258 Section 14 Serial Communication Interface 3 (SCI3) 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 259 Section 15 I C Bus Interface 2 (IIC2) Section 15 I C Bus Interface 2 (IIC2) The I C bus interface 2 conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however.
Page 260 Section 15 I C Bus Interface 2 (IIC2) Transfer clock generation circuit Transmission/ ICCR1 reception control circuit Output ICCR2 control ICMR Noise canceler ICDRT Output ICDRS control Address Noise canceler comparator ICDRR Bus state decision circuit Arbitration ICSR decision circuit ICIER Interrupt [Legend]...
Page 261 Section 15 I C Bus Interface 2 (IIC2) SCL in SCL out SDA in SDA out (Master) SCL in SCL in SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 15.2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I...
Page 262 Section 15 I C Bus Interface 2 (IIC2) • I C bus transmit data register (ICDRT) • I C bus receive data register (ICDRR) • I C bus shift register (ICDRS) 15.3.1 C Bus Control Register 1 (ICCR1) ICCR1 enables or disables the I C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Page 263 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description CKS3 Transfer Clock Select 3 to 0 CKS2 These bits should be set according to the necessary transfer rate (see table 15.2) in master mode. In slave CKS1 mode, these bits are used for reservation of the setup time CKS0...
Page 264 Section 15 I C Bus Interface 2 (IIC2) 15.3.2 C Bus Control Register 2 (ICCR2) ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I C bus interface 2. Initial Bit Name Value...
Page 265 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description SDAOP SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction.
Page 266 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description   5, 4 All 1 Reserved These bits are always read as 1, and cannot be modified. BCWP BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction.
Page 267 Section 15 I C Bus Interface 2 (IIC2) 15.3.4 C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Initial Bit Name Value Description Transmit Interrupt Enable...
Page 268 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description STIE Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled. ACKE Acknowledge Bit Judgement Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed.
Page 269 Section 15 I C Bus Interface 2 (IIC2) 15.3.5 C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status. Initial Bit Name Value Description TDRE Transmit Data Register Empty [Setting conditions] • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty •...
Page 270 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description NACKF No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is [Clearing condition] •...
Page 271 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description AL/OVE Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master mode with the I C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format.
Page 272 Section 15 I C Bus Interface 2 (IIC2) 15.3.6 Slave Address Register (SAR) SAR selects the communication format and sets the slave address. When the chip is in slave mode with the I C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device.
Page 273 Section 15 I C Bus Interface 2 (IIC2) 15.3.7 C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data.
Page 274 Section 15 I C Bus Interface 2 (IIC2) 15.4 Operation The I C bus interface can communicate either in I C bus mode or clocked synchronous serial mode by setting FS in SAR. 15.4.1 C Bus Format Figure 15.3 shows the I C bus formats.
Page 275 Section 15 I C Bus Interface 2 (IIC2) R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. Acknowledge.
Page 276 Section 15 I C Bus Interface 2 (IIC2) (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Master output) Slave address (Slave output) TDRE TEND ICDRT Address + R/W Data 1 Data 2 ICDRS...
Page 277 Section 15 I C Bus Interface 2 (IIC2) 15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 15.7 and 15.8.
Page 278 Section 15 I C Bus Interface 2 (IIC2) Master transmit mode Master receive mode (Master output) (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (Slave output) TDRE TEND RDRF ICDRS Data 1...
Page 279 Section 15 I C Bus Interface 2 (IIC2) (Master output) (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Slave output) RDRF RCVD ICDRS Data n-1 Data n ICDRR Data n Data n-1 User [7] Read ICDRR,...
Page 280 Section 15 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode (Master output) (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (Slave output) TDRE TEND ICDRT...
Page 281 Section 15 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode (Master output) (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Slave output) TDRE TEND ICDRT ICDRS Data n...
Page 282 Section 15 I C Bus Interface 2 (IIC2) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame.
Page 283 Section 15 I C Bus Interface 2 (IIC2) 15.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected.
Page 284 Section 15 I C Bus Interface 2 (IIC2) Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 0 Bit 1 (Output) TDRE Data 1 ICDRT Data 2 Data 3 Data 1 Data 2 Data 3 ICDRS User [3] Write data [3] Write data...
Page 285 Section 15 I C Bus Interface 2 (IIC2) Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 0 Bit 1 (Input) RDRF Data 1 Data 2 Data 3 ICDRS Data 2 ICDRR Data 1 User [2] Set MST [3] Read ICDRR [3] Read ICDRR processing...
Page 286 Section 15 I C Bus Interface 2 (IIC2) 15.4.8 Example of Use Flowcharts in respective modes that use the I C bus interface are shown in figures 15.17 to 15.20. Start Initialize Test the status of the SCL and SDA lines. Read BBSY in ICCR2 Set master transmit mode.
Page 287 Section 15 I C Bus Interface 2 (IIC2) Mater receive mode Clear TEND, select master receive mode, and then clear TDRE.* Clear TEND in ICSR Set acknowledge to the transmit device.* Clear TRS in ICCR1 to 0 Dummy-read ICDDR.* Clear TDRE in ICSR Wait for 1 byte to be received Clear ACKBT in ICIER to 0 Check whether it is the (last receive - 1).
Page 288 Section 15 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. Write transmit data in ICDRT [4] Set the last byte of transmit data.
Page 289 Section 15 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [2] Set acknowledge to the transmit device. Clear ACKBT in ICIER to 0 [3] Dummy-read ICDRR. Dummy-read ICDRR [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1).
Page 290 Section 15 I C Bus Interface 2 (IIC2) 15.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun. Table 15.3 shows the contents of each interrupt request.
Page 291 Section 15 I C Bus Interface 2 (IIC2) 15.6 Bit Synchronous Circuit In master mode,this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device •...
Page 292 Section 15 I C Bus Interface 2 (IIC2) 15.7 Usage Notes 15.7.1 Issue (Retransmission) of Start/Stop Conditions In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed.
Page 293 Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1.
Page 294 Section 16 A/D Converter Module data bus Internal data bus 10-bit D/A φ/4 Control circuit φ/8 Comparator Sample-and- hold circuit interrupt ADTRG [Legend] A/D control register ADCR: A/D control/status register ADCSR: A/D data register A ADDRA: A/D data register B ADDRB: A/D data register C ADDRC:...
Page 295 Section 16 A/D Converter 16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1.
Page 296 Section 16 A/D Converter 16.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D control/status register (ADCSR) •...
Page 297 Section 16 A/D Converter 16.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter. Initial Bit Name Value Description A/D End Flag [Setting conditions] • When A/D conversion ends in single mode •...
Page 298 Section 16 A/D Converter Initial Bit Name Value Description Channel Select 2 to 0 Select analog input channels. When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4...
Page 299 Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed.
Page 300 Section 16 A/D Converter 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) has passed after the ADST bit is set to 1, then starts conversion.
Page 301 Section 16 A/D Converter Table 16.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol A/D conversion start delay time — — Input sampling time — — — — A/D conversion time — — CONV Note: All values represent the number of states. 16.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
Page 302 Section 16 A/D Converter 16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). •...
Page 303 Section 16 A/D Converter Digital output Ideal A/D conversion characteristic Quantization error Analog input voltage Figure 16.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 16.5 A/D Conversion Accuracy Definitions (2) Rev.5.00 Nov.
Page 304 Section 16 A/D Converter 16.6 Usage Notes 16.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 305 Section 17 EEPROM Section 17 EEPROM The H8/3694N has an on-chip 512-byte EEPROM. The block diagram of the EEPROM is shown in figure 17.1. 17.1 Features • Two writing methods: 1-byte write Page write: Page size 8 bytes • Three reading methods:...
Page 306 Section 17 EEPROM EEPROM Data bus H'FF10 EEPROM Key Y-select/ register (EKR) Sense amp. Memory array Key control circuit H'0000 User area (512 bytes) H'01FF C bus interface control circuit Slave address H'FF09 register ESAR Power-on reset Booster circuit EEPROM module [Legend] ESAR: Register for referring the slave address (specifies the slave address of the memory array)
Page 307 Section 17 EEPROM 17.2 Input/Output Pins Pins used in the EEPROM are listed in table 17.1. Table 17.1 Pin Configuration Pin name Symbol Input/Output Function Serial clock pin Input The SCL pin is used to control serial input/output data timing. The data is input at the rising edge of the clock and output at the falling edge of the clock.
Page 308 Section 17 EEPROM 17.4 Operation 17.4.1 EEPROM Interface The HD64N3694G has a multi-chip structure with two internal chips of the HD64F3694G (F- ZTAT™ version) and 512-byte EEPROM. The HD6483694G has a multi-chip structure with two internal chips of the HD6433694G (mask-ROM version) and 512-byte EEPROM. The EEPROM interface is the I C bus interface.
Page 309 Section 17 EEPROM 17.4.4 Stop Condition A low-to-high transition of the SDA input with the SCL input high is needed to generate the stop condition for stopping read, write operation. The standby operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in an internally- timed write cycle to the memories.
Page 310 Section 17 EEPROM The initial value of the slave address code written in the EEPROM is H'00. It can be written in the range of H'00 to H'07. Be sure to write the data by the byte write method. The next one bit of the slave address is the R/W code. 0 is for a write and 1 is for a read. The EEPROM turns to a standby state if the device code is not "1010"...
Page 311 Section 17 EEPROM 17.4.7 Write Operations There are two types write operations; byte write operation and page write operation. To initiate the write operation, input 0 to R/W code following the slave address. 1. Byte Write A write operation requires an 8-bit data of a 7-bit slave address with R/W code = "0". Then the EEPROM sends acknowledgement "0"...
Page 312 Section 17 EEPROM Addresses in the page are incremented at each receipt of the write data and the write data can be input up to 8 bytes. If the LSB 3 bits (A2 to A0) in the EEPROM address reach the last address of the page, the address will roll over to the first address of the same page.
Page 313 Section 17 EEPROM 17.4.9 Read Operation There are three read operations; current address read, random address read, and sequential read. Read operations are initiated in the same way as write operations with the exception of R/W = 1. 1. Current Address Read The internal address counter maintains the (n+1) address that is made by the last address (n) accessed during the last read or write operation, with incremented by one.
Page 314 Section 17 EEPROM 2. Random Address Read This is a read operation with defined read address. A random address read requires a dummy write to set read address. The EEPROM receives a start condition, slave address + R/W code (R/W = 0), memory address (upper) and memory address (lower) sequentially. The EEPROM outputs acknowledgement "0"...
Page 315 Section 17 EEPROM Slave address R/W ACK Read Data Read Data · · · · Start Stop condition conditon [Legend] R/W: R/W code (0 is for a write and 1 is for a read) ACK: acknowledge Figure 17.7 Sequential Read Operation (when current address read is used) Rev.5.00 Nov.
Page 316 Section 17 EEPROM 17.5 Usage Notes 17.5.1 Data Protection at V On/Off When V is turned on or off, the data might be destroyed by malfunction. Be careful of the notices described below to prevent the data to be destroyed. 1.
Page 317 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) This LSI can include a power-on reset circuit and low-voltage detection circuit as optional circuits. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits.
Page 318 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) φ Internal reset Noise canceler signal Power-on reset circuit Noise canceler LVDCR Vreset Ladder − resistor LVDRES Vint Interrupt LVDSR − control LVDINT circuit Reference voltage Interrupt generator request Low-voltage detection circuit [Legend] PSS: Prescaler S...
Page 319 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Table 18.1 shows the relationship between the LVDCR settings and select functions. LVDCR should be set according to table 18.1. Initial Bit Name Value Description LVDE LVD Enable 0: The low-voltage detection circuit is not used (In standby mode) 1: The low-voltage detection circuit is used ...
Page 320 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Table 18.1 LVDCR Settings and Select Functions LVDCR Settings Select Functions Low-Voltage- Low-Voltage- Detection Detection Power-On Falling Rising Reset LVDE LVDSEL LVDRE LVDDE LVDUE LVDR Interrupt Interrupt     ...
Page 321 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) 18.3 Operation 18.3.1 Power-On Reset Circuit Figure 18.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ.
Page 322 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) PWON Vpor PSS-reset signal Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 18.2 Operational Timing of Power-On Reset Circuit 18.3.2 Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detect) Circuit: Figure 18.3 shows the timing of the LVDR function.
Page 323 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Vreset LVDRmin LVDRES PSS-reset signal Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 18.3 Operational Timing of LVDR Circuit LVDI (Interrupt by Low Voltage Detect) Circuit: Figure 18.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled.
Page 324 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated. If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function is performed.
Page 325 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Procedures for Clearing Settings when Using LVDR and LVDI: To operate or release the low-voltage detection circuit normally, follow the procedure described below. Figure 18.5 shows the timing for the operation and release of the low-voltage detection circuit.
Page 326 Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Rev.5.00 Nov. 02, 2005 Page 298 of 418 REJ09B0028-0500...
Page 327 Section 19 Power Supply Circuit Section 19 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external V pin.
Page 328 Section 19 Power Supply Circuit 19.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the V pin and V pin, as shown in figure 19.2. The external power supply is then input directly to the internal power supply.
Page 329 Section 20 List of Registers Section 20 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below.
Page 330 Section 20 List of Registers 20.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Note: Access to undefined or reserved addresses should not take place.
Page 331 Section 20 List of Registers Data Abbre- Module Access Register Name viation Address Name Width State General register B H'FF8A Timer W General register C H'FF8C Timer W General register D H'FF8E Timer W Flash memory control register 1 FLMCR1 8 H'FF90 Flash memory control register 2 FLMCR2 8...
Page 332 Section 20 List of Registers Data Abbre- Module Access Register Name viation Address Name Width State A/D data register B ADDRB H'FFB2 converter A/D data register C ADDRC H'FFB4 converter A/D data register D ADDRD H'FFB6 converter A/D control/status register ADCSR H'FFB8 converter...
Page 333 Section 20 List of Registers Data Abbre- Module Access Register Name viation Address Name Width State Port pull-up control register 1 PUCR1 H'FFD0 I/O port Port pull-up control register 5 PUCR5 H'FFD1 I/O port H'FFD2, I/O port — — — —...
Page 334 Section 20 List of Registers Data Abbre- Module Access Register Name viation Address Name Width State System control register 1 SYSCR1 8 H'FFF0 Power-down System control register 2 SYSCR2 8 H'FFF1 Power-down Interrupt edge select register 1 IEGR1 H'FFF2 Interrupts Interrupt edge select register 2 IEGR2 H'FFF3...
Page 335 Section 20 List of Registers 20.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row. Register Module Name Bit 7 Bit 6 Bit 5...
Page 336 Section 20 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name FLMCR1 — FLMCR2 FLER — — — — — — — FLPWCR PDWND — — —...
Page 337 Section 20 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name TMWD — — — — CKS3 CKS2 CKS1 CKS0 WDT* — — — — — —...
Page 338 Section 20 List of Registers • EEPROM Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name EEPROM Notes: 1. LVDC: Low-voltage detection circuits (optional) 2. WDT: Watchdog timer 3. These bits are reserved in the EEPROM stacked F-ZTAT and mask-ROM versions.
Page 339 Section 20 List of Registers 20.3 Registers States in Each Operating Mode Register Name Reset Active Sleep Subactive Subsleep Standby Module — — — — — Initialized LVDC LVDCR — — — — — Initialized (optional)* LVDSR — — — —...
Page 340 Section 20 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module — — TCNTV Initialized Initialized Initialized Initialized Timer V — — TCRV1 Initialized Initialized Initialized Initialized — — — — — Initialized Timer A — — —...
Page 341 Section 20 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module — — — — — PMR1 Initialized I/O port — — — — — PMR5 Initialized — — — — — PCR1 Initialized — — — —...
Page 342 Section 20 List of Registers Rev.5.00 Nov. 02, 2005 Page 314 of 418 REJ09B0028-0500...
Page 343 Section 21 Electrical Characteristics Section 21 Electrical Characteristics 21.1 Absolute Maximum Ratings Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Input voltage Ports other than ports –0.3 to V +0.3 B and X1...
Page 344 Section 21 Electrical Characteristics Power Supply Voltage and Operating Frequency Range φ (MHz) φ (kHz) 20.0 16.384 10.0 8.192 4.096 • AV = 3.3 to 5.5 V • AV = 3.3 to 5.5 V • Active mode • Subactive mode •...
Page 345 Section 21 Electrical Characteristics Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used φosc (MHz) 20.0 16.0 Vcc(V) Operation guarantee range Operation guarantee range except A/D conversion accuracy Rev.5.00 Nov. 02, 2005 Page 317 of 418 REJ09B0028-0500...
Page 346 Section 21 Electrical Characteristics 21.2.2 DC Characteristics Table 21.2 DC Characteristics (1) = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Unit Notes RES, NMI, ×...
Page 347 Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Unit Notes Output P10 to P12, = 4.0 to 5.5 V – 1.0 — — high P14 to P17, –I = 1.5 mA voltage P20 to P22, P50 to P55, –I = 0.1 mA –...
Page 348 Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Unit Notes Pull-up –I P10 to P12, = 5.0 V, 50.0 — 300.0 µA P14 to P17, = 0.0 V current P50 to P55 = 3.0 V, — 60.0 —...
Page 349 Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Unit Notes Subsleep = 3.0 V — 30.0 50.0 µA SUBSP mode 32-kHz crystal current resonator = φ consump- (φ tion Standby 32-kHz crystal — — µA STBY mode resonator not current used...
Page 350 EESTBY µs (at standby) Note: The current consumption of the EEPROM chip is shown. For the current consumption of H8/3694N, add the above current values to the current consumption of H8/3694F. Rev.5.00 Nov. 02, 2005 Page 322 of 418 REJ09B0028-0500...
Page 351 Section 21 Electrical Characteristics Table 21.2 DC Characteristics (3) = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Item Symbol Pins Unit Test Condition Allowable output low Output pins = 4.0 to 5.5 V — —...
Page 352 Section 21 Electrical Characteristics 21.2.3 AC Characteristics Table 21.3 AC Characteristics = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Reference Item Symbol Pins Test Condition Unit Figure System clock OSC1, OSC2 V = 4.0 to 5.5 V —...
Page 353 Section 21 Electrical Characteristics Values Applicable Reference Item Symbol Pins Test Condition Unit Figure NMI, Input pin high — — Figure 21.3 IRQ0 to width subcyc IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD NMI, Input pin low —...
Page 354 Section 21 Electrical Characteristics Table 21.4 I C Bus Interface Timing = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Reference Item Symbol Condition Min Unit Figure SCL input cycle time + 600 —...
Page 355 Section 21 Electrical Characteristics Table 21.5 Serial Communication Interface (SCI) Timing = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Reference Item Symbol Pins Test Condition Typ Max Unit Figure Input Asynchro- SCK3...
Page 356 Section 21 Electrical Characteristics 21.2.4 A/D Converter Characteristics Table 21.6 A/D Converter Characteristics = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Test Reference Item Symbol Pins Condition Typ Max Unit Figure Analog power supply...
Page 357 Section 21 Electrical Characteristics Values Applicable Test Reference Item Symbol Pins Condition Typ Max Unit Figure Conversion time = 4.0 to — — (single mode) 5.5 V Nonlinearity error — — ±3.5 Offset error — — ±3.5 Full-scale error — —...
Page 358 Section 21 Electrical Characteristics 21.2.6 Flash Memory Characteristics Table 21.8 Flash Memory Characteristics = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Unit Programming time (per 128 bytes)* —...
Page 359 Section 21 Electrical Characteristics Values Test Item Symbol Condition Unit Erasing Wait time after SWE — — µs bit setting* Wait time after ESU — — µs bit setting* Wait time after E bit — setting* α Wait time after E bit clear* —...
Page 360 Section 21 Electrical Characteristics 21.2.7 EEPROM Characteristics Table 21.9 EEPROM Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Test Reference Item Symbol Condition Min Typ Max Unit Figure ...
Page 361 Section 21 Electrical Characteristics 21.2.8 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 21.10 Power-Supply-Voltage Detection Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Unit Power-supply falling detection Vint (D) LVDSEL = 0 —...
Page 362 Section 21 Electrical Characteristics 21.2.9 Power-On Reset Circuit Characteristics (Optional) Table 21.11 Power-On Reset Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Item Symbol Test Condition Min Unit Pull-up resistance of RES pin — kΩ...
Page 363 Section 21 Electrical Characteristics Power Supply Voltage and Operating Frequency Range φ (MHz) φ (kHz) 20.0 16.384 10.0 8.192 4.096 • AV = 3.0 to 5.5 V • AV = 3.0 to 5.5 V • Active mode • Subactive mode •...
Page 364 Section 21 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range φ (MHz) 20.0 10.0 • V = 2.7 to 5.5 V • Active mode • Sleep mode Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used φosc (MHz) 20.0...
Page 365 Section 21 Electrical Characteristics 21.3.2 DC Characteristics Table 21.12 DC Characteristics (1) = 2.7 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Unit Notes RES, NMI, ×...
Page 366 Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Unit Notes Output P10 to P12, = 4.0 to 5.5 V – 1.0 — — high P14 to P17, –I = 1.5 mA voltage P20 to P22, P50 to P55, –I = 0.1 mA –...
Page 367 Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Unit Notes Pull-up –I P10 to P12, = 5.0 V, 50.0 — 300.0 µA P14 to P17, = 0.0 V current P50 to P55 = 3.0 V, — 60.0 —...
Page 368 Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Unit Notes Subsleep = 3.0 V — 30.0 50.0 µA SUBSP mode 32-kHz crystal current resonator = φ consump- (φ tion Standby 32-kHz crystal — — µA STBY mode resonator not used current consump-...
Page 369 EESTBY µs (at standby) Note: The current consumption of the EEPROM chip is shown. For the current consumption of H8/3694N, add the above current values to the current consumption of H8/3694. Rev.5.00 Nov. 02, 2005 Page 341 of 418 REJ09B0028-0500...
Page 370 Section 21 Electrical Characteristics Table 21.12 DC Characteristics (3) = 2.7 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Item Symbol Pins Unit Test Condition Allowable output low Output pins except port = 4.0 to 5.5 V —...
Page 371 Section 21 Electrical Characteristics 21.3.3 AC Characteristics Table 21.13 AC Characteristics = 2.7 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Reference Item Symbol Pins Test Condition Unit Figure System clock OSC1, = 4.0 to 5.5 V —...
Page 372 Section 21 Electrical Characteristics Values Applicable Reference Item Symbol Pins Test Condition Unit Figure NMI, Input pin high — — Figure 21.3 IRQ0 to width subcyc IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD NMI, Input pin low —...
Page 373 Section 21 Electrical Characteristics Table 21.14 I C Bus Interface Timing = 2.7 V to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise specified. Values Test Reference Item Symbol Condition Min Unit Figure SCL input cycle time + 600 —...
Page 374 Section 21 Electrical Characteristics Table 21.15 Serial Communication Interface (SCI) Timing = 2.7 V to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Test Condition Typ Max Unit Figure Input Asynchro-...
Page 375 Section 21 Electrical Characteristics 21.3.4 A/D Converter Characteristics Table 21.16 A/D Converter Characteristics = 2.7 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Test Reference Item Symbol Pins Condition Unit Figure Analog power supply voltage Analog input voltage AV...
Page 376 Section 21 Electrical Characteristics Values Applicable Test Reference Item Symbol Pins Condition Unit Figure Conversion time = 4.0 to 5.5 V 134 — — (single mode) Nonlinearity error — — ±3.5 Offset error — — ±3.5 Full-scale error — — ±3.5 Quantization error —...
Page 377 Section 21 Electrical Characteristics 21.3.6 EEPROM Characteristics Table 21.18 EEPROM Characteristics = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise indicated. Values Test Reference Item Symbol Condition Min Typ Max Unit Figure ...
Page 378 Section 21 Electrical Characteristics 21.3.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 21.19 Power-Supply-Voltage Detection Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Condition Item Symbol Unit Power-supply falling detection Vint (D) LVDSEL = 0 —...
Page 379 Section 21 Electrical Characteristics 21.3.8 Power-On Reset Circuit Characteristics (Optional) Table 21.20 Power-On Reset Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Condition Item Symbol Unit Pull-up resistance of RES pin — kΩ Power-on reset start voltage* —...
Page 380 Section 21 Electrical Characteristics × 0.7 OSC1 Figure 21.2 RES Low Width Timing IRQ0 to IRQ3 WKP0 to WKP5 ADTRG FTCI FTIOA to FTIOD TMCIV, TMRIV TRGV Figure 21.3 Input Timing STAH STOS SCLH STAS SCLL SDAS SDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition...
Page 381 Section 21 Electrical Characteristics SCKW SCK3 Scyc Figure 21.5 SCK3 Input Clock Timing Scyc or V SCK3 or V (transmit data) (receive data) Note: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Load conditions are shown in figure 21.8. Figure 21.6 SCI Input/Output Timing in Clocked Synchronous Mode Rev.5.00 Nov.
Page 382 Section 21 Electrical Characteristics SCLH SCLL STAS SDAH STOS STAH SDAS (in) (out) Figure 21.7 EEPROM Bus Timing 21.5 Output Load Condition 2.4 kΩ LSI output pin 12 k Ω 30 pF Figure 21.8 Output Load Circuit Rev.5.00 Nov. 02, 2005 Page 354 of 418 REJ09B0028-0500...
Page 383 Appendix Appendix A Instruction Set Instruction List Condition Code Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand...
Page 384 Appendix Condition Code Notation (cont) Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev.5.00 Nov. 02, 2005 Page 356 of 418 REJ09B0028-0500...
Page 385 Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation #xx:8 → Rd8 MOV.B #xx:8, Rd — — — Rs8 → Rd8 MOV.B Rs, Rd — — — @ERs →...
Page 386 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–2 → ERd32 MOV.W Rs, @–ERd — — — Rs16 → @ERd Rs16 → @aa:16 MOV.W Rs, @aa:16 — — — Rs16 → @aa:24 MOV.W Rs, @aa:24 —...
Page 387 Appendix 2. Arithmetic Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — Rd8+Rs8 → Rd8 ADD.B Rs, Rd — Rd16+#xx:16 → Rd16 ADD.W #xx:16, Rd — Rd16+Rs16 → Rd16 ADD.W Rs, Rd —...
Page 388 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–1 → ERd32 DEC.L #1, ERd — — — ERd32–2 → ERd32 DEC.L #2, ERd — — — DAS.Rd Rd8 decimal adjust — — → Rd8 Rd8 ×...
Page 389 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation 0–Rd8 → Rd8 NEG.B Rd — 0–Rd16 → Rd16 NEG.W Rd — 0–ERd32 → ERd32 NEG.L ERd — 0 → (<bits 15 to 8> EXTU EXTU.W Rd —...
Page 390 Appendix 3. Logic Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — — Rd16∧#xx:16 → Rd16 AND.W #xx:16, Rd —...
Page 391 Appendix 4. Shift Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation SHAL.B Rd — — SHAL SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR SHAR.W Rd — — SHAR.L ERd —...
Page 392 Appendix 5. Bit-Manipulation Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — BSET (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
Page 393 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 — — — — — ¬...
Page 394 Appendix 6. Branching Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Branch Condition BRA d:8 (BT d:8) — If condition Always — — — — — — is true then BRA d:16 (BT d:16) —...
Page 395 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC ← ERn JMP @ERn — — — — — — — PC ← aa:24 JMP @aa:24 — — — — — — — PC ← @aa:8 JMP @@aa:8 —...
Page 396 Appendix 7. System Control Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC → @–SP TRAPA #x:2 — — — — — — TRAPA CCR → @–SP <vector> → PC CCR ← @SP+ — PC ←...
Page 397 Appendix 8. Block Transfer Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation if R4L ≠ 0 then EEPMOV. B — — — — — — — EEPMOV repeat @R5 → @R6 R5+1 → R5 R6+1 →...
Page 398 Appendix Operation Code Map Table A.2 Operation Code Map (1) Rev.5.00 Nov. 02, 2005 Page 370 of 418 REJ09B0028-0500...
Page 399 Appendix Table A.2 Operation Code Map (2) Rev.5.00 Nov. 02, 2005 Page 371 of 418 REJ09B0028-0500...
Page 400 Appendix Table A.2 Operation Code Map (3) Rev.5.00 Nov. 02, 2005 Page 372 of 418 REJ09B0028-0500...
Page 401 Appendix Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write.
Page 402 Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation Byte data access 2 or 3* Word data access 2 or 3* Internal operation Note: Depends on which on-chip peripheral module is accessed.
Page 403 Appendix Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDS #1/2/4, ERd...
Page 404 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16...
Page 405 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BIOR BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD #xx:3, Rd...
Page 406 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP.B #xx:8, Rd...
Page 407 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR...
Page 408 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd...
Page 409 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd NEG.L ERd NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8, Rd...
Page 410 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd...
Page 411 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd TRAPA TRAPA #xx:2 XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC...
Page 412 Appendix Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes Addressing Mode Functions Instructions Data — — — — transfer POP, PUSH — — — — — — — — — — — — instructions MOVFPE, —...
Page 413 Appendix Appendix B I/O Port Block Diagrams I/O Port Block Diagrams RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus PUCR Pull-up MOS TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR:...
Page 414 Appendix Internal data bus PUCR Pull-up MOS [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P16 to P14) Rev.5.00 Nov. 02, 2005 Page 386 of 418 REJ09B0028-0500...
Page 415 Appendix Internal data bus PUCR Pull-up MOS [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.3 Port 1 Block Diagram (P12, P11) Rev.5.00 Nov. 02, 2005 Page 387 of 418 REJ09B0028-0500...
Page 416 Appendix Internal data bus PUCR Pull-up MOS Timer A TMOW [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.4 Port 1 Block Diagram (P10) Rev.5.00 Nov. 02, 2005 Page 388 of 418 REJ09B0028-0500...
Page 417 Appendix Internal data bus SCI3 [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.5 Port 2 Block Diagram (P22) Rev.5.00 Nov. 02, 2005 Page 389 of 418 REJ09B0028-0500...
Page 418 Appendix Internal data bus SCI3 [Legend] PDR: Port data register PCR: Port control register Figure B.6 Port 2 Block Diagram (P21) Rev.5.00 Nov. 02, 2005 Page 390 of 418 REJ09B0028-0500...
Page 419 Appendix SCI3 SCKIE SCKOE Internal data bus SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.7 Port 2 Block Diagram (P20) Rev.5.00 Nov. 02, 2005 Page 391 of 418 REJ09B0028-0500...
Page 420 PDR: Port data register PCR: Port control register Figure B.8 Port 5 Block Diagram (P57, P56)* Note: * This diagram is applied to the SCL and SDA pins in the H8/3694N. Rev.5.00 Nov. 02, 2005 Page 392 of 418 REJ09B0028-0500...
Page 421 Appendix Internal data bus PUCR Pull-up MOS ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.9 Port 5 Block Diagram (P55) Rev.5.00 Nov. 02, 2005 Page 393 of 418 REJ09B0028-0500...
Page 422 Appendix Internal data bus PUCR Pull-up MOS [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.10 Port 5 Block Diagram (P54 to P50) Rev.5.00 Nov. 02, 2005 Page 394 of 418 REJ09B0028-0500...
Page 423 Appendix Internal data bus Timer V TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.11 Port 7 Block Diagram (P76) Rev.5.00 Nov. 02, 2005 Page 395 of 418 REJ09B0028-0500...
Page 424 Appendix Internal data bus Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.12 Port 7 Block Diagram (P75) Rev.5.00 Nov. 02, 2005 Page 396 of 418 REJ09B0028-0500...
Page 425 Appendix Internal data bus Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.13 Port 7 Block Diagram (P74) Rev.5.00 Nov. 02, 2005 Page 397 of 418 REJ09B0028-0500...
Page 426 Appendix Internal data bus [Legend] PDR: Port data register PCR: Port control register Figure B.14 Port 8 Block Diagram (P87 to P85) Rev.5.00 Nov. 02, 2005 Page 398 of 418 REJ09B0028-0500...
Page 427 Appendix Internal data bus Timer W Output control signals A to D FTIOA FTIOB FTIOC FTIOD [Legend] PDR: Port data register PCR: Port control register Figure B.15 Port 8 Block Diagram (P84 to P81) Rev.5.00 Nov. 02, 2005 Page 399 of 418 REJ09B0028-0500...
Page 428 Appendix Internal data bus Timer W FTCI [Legend] PDR: Port data register PCR: Port control register Figure B.16 Port 8 Block Diagram (P80) Rev.5.00 Nov. 02, 2005 Page 400 of 418 REJ09B0028-0500...
Page 429 High impedance impedance impedance impedance impedance impedance Notes: 1. High level output when the pull-up MOS is in on state. 2. The P55 to P50 pins are applied to the H8/3694N. Rev.5.00 Nov. 02, 2005 Page 401 of 418 REJ09B0028-0500...
Page 430 Appendix Appendix C Product Code Lineup Product Classification Product Code Model Marking Package Code H8/3694 Flash memory Standard HD64F3694H HD64F3694H QFP-64 (FP-64A) version product HD64F3694FP HD64F3694FP LQFP-64 (FP-64E) HD64F3694FX HD64F3694FX LQFP-48 (FP-48F) HD64F3694FY HD64F3694FY LQFP-48 (FP-48B) HD64F3694FT HD64F3694FT QFN-48(TNP-48) Product with HD64F3694GH HD64F3694GH QFP-64 (FP-64A)
Page 431 Appendix Product Classification Product Code Model Marking Package Code H8/3692 Mask ROM Standard HD6433692H HD6433692(***)H QFP-64 (FP-64A) version product HD6433692FP HD6433692(***)FP LQFP-64 (FP-64E) HD6433692FX HD6433692(***)FX LQFP-48 (FP-48F) HD6433692FY HD6433692(***)FY LQFP-48 (FP-48B) HD6433692FT HD6433692(***)FT QFN-48(TNP-48) Product with HD6433692GH HD6433692G(***)H QFP-64 (FP-64A) POR &...
Page 432 Appendix Product Classification Product Code Model Marking Package Code H8/3694N EEPROM Flash Product with HD64N3694GFP HD64N3694GFP LQFP-64 (FP-64E) stacked memory POR & LVDC version version Mask HD6483694GFP HD6483694G(***)FP LQFP-64 (FP-64E) version Legend: (***): ROM code. POR & LVDC: Power-on reset and low-voltage detection circuits.
Page 433 Appendix Appendix D Package Dimensions The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority. Figure D.1 FP-64E Package Dimensions Rev.5.00 Nov. 02, 2005 Page 405 of 418 REJ09B0028-0500...
Page 434 Appendix Figure D.2 FP-64A Package Dimensions Rev.5.00 Nov. 02, 2005 Page 406 of 418 REJ09B0028-0500...
Page 435 Appendix Figure D.3 FP-48F Package Dimensions Rev.5.00 Nov. 02, 2005 Page 407 of 418 REJ09B0028-0500...
Page 436 Appendix Figure D.4 FP-48B Package Dimensions Rev.5.00 Nov. 02, 2005 Page 408 of 418 REJ09B0028-0500...
Page 437 Appendix Figure D.5 TNP-48 Package Dimensions Rev.5.00 Nov. 02, 2005 Page 409 of 418 REJ09B0028-0500...
Page 438 Appendix Appendix E EEPROM Stacked-Structure Cross-Sectional View Figure E.1 EEPROM Stacked-Structure Cross-Sectional View Rev.5.00 Nov. 02, 2005 Page 410 of 418 REJ09B0028-0500...
Page 439 Group of F-ZTAT PB1/AN1 POR/LVD converter (optional) PB2/AN2 and Mask-ROM Versions, PB3/AN3 PB4/AN4 Figure 1.2 Internal Block PB5/AN5 Diagram of H8/3694N Data bus (upper) PB6/AN6 PB7/AN7 (EEPROM Stacked Address bus Version) Rev.5.00 Nov. 02, 2005 Page 411 of 418 REJ09B0028-0500...
Page 440 Item Page Revision (See Manual for Details) Section 5 Clock Pulse Generators Figure 5.3 Typical Connection to Crystal C = C = 10 to 22 pF Resonator Figure 5.5 Typical Connection to Ceramic Resonator = 5 to 30 pF = 5 to 30 pF Section 6 Power-Down Bit Name Description Modes...
Page 441 Item Page Revision (See Manual for Details) Section 15 I C Bus Bit Name Description Interface 2 (IIC2) STOP Stop Condition Detection Flag 15.3.5 I C Bus Status Register (ICSR) [Setting conditions] • In master mode, when a stop condition is detected after frame transfer •...
Page 442 Item Page Revision (See Manual for Details) RES Pin Table 21.2 DC Mode Internal State Characteristics (1) Active mode 1 Operates Active mode 2 Operates (φOSC/64) Sleep mode 1 Only timers operate Sleep mode 2 Only timers operate (φOSC/64) Table 21.12 DC Values Applicable Characteristics (1)
Page 443 Index Random address read ......286 Sequential read........286 A/D converter ......... 265 Slave address reference register Sample-and-hold circuit...... 272 (ESAR)..........281 Scan mode........... 271 Slave addressing........281 Single mode ........271 Start condition........280 Address break ........... 63 Stop condition ........281 Addressing modes........
Page 444 I/O port block diagrams ...... 385 C bus data format ......... 246 Memory map..........14 C bus interface 2 (IIC2) ....... 231 Module standby function ......86 Acknowledge........247 Bit synchronous circuit....... 263 Clocked synchronous serial format..255 Noise canceler ........257 On-board programming modes ....
Page 445 EBR1 ......91, 303, 308, 311 PUCR5 ......120, 305, 309, 312 EKR ......279, 306, 310, 313 RDR ......192, 303, 308, 312 FENR......92, 303, 308, 311 RSR............. 192 FLMCR1....... 89, 303, 308, 311 SAR......244, 302, 307, 311 FLMCR2.......
Page 446 221 Overrun error ........209 Parity error.......... 209 Stacked-structure cross sectional Vector address........... 49 view of H8/3694N ........410 Stack pointer (SP)........19 Watchdog timer........183 Timer A ..........131 Rev.5.00 Nov. 02, 2005 Page 418 of 418 REJ09B0028-0500...
Page 447 Publication Date: 1st Edition, Jul, 2001 Rev.5.00, Nov. 02, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2005. Renesas Technology Corp. All rights reserved. Printed in Japan.
Page 448 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501...
Page 450 H8/3694 Group Hardware Manual...

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