Hitachi H8S/2633 Hardware Manual page 1116

Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagram
P1n
Internal address bus
Legend
WDDR1 : Write to P1DDR
WDR1 : Write to P1DR
RDR1 : Read P1DR
RPOR1 : Read port 1
n= 0, 1
Note: *
Priority order: Address output > Output compare output > PWM output > DMA transfer acknowledge output >
Figure C-1 (a) Port 1 Block Diagram (Pins P10 and P11)
1104
*
pulse output > DR output
Reset
R
Q D
P1nDDR
C
WDDR1
Reset
R
Q D
System controller
P1nDR
C
WDR1
PPG module
DMA controller
TPU module
RDR1
RPOR1
Address output enable
Pulse output enable
Pulse output
DMA transfer
acknowledge enable
DMA transfer acknowledge
Output compare
Output/PWM output enable
Output compare output/
PWM output
Input capture input