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TCSR1—Timer Control/Status Register 1
Bit
:
7
OVF
Initial value
:
0
R/(W) *
R/W
:
Timer mode select
Overflow flag
0 [Clearing]
(1) When 0 is written to TME bit;
(2) When 0 is written to OVF bit after reading TCSR when OVF=1.
1 [Setting]
When TCNT overflows (H'FF→ H'00).
When internal reset request generation is selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
Notes:
TCSR is write-protected by a password to prevent accidental overwriting.
For details see section 15.2.5, Notes on Register Access.
* Only 0 can be written to these bits (to clear these flags).
6
5
4
WT/IT
TME
PSS
0
0
0
R/W
R/W
R/W
Reset or NMI
0 NMI interrupt request
1 Internal reset request
Prescaler select
0 TCNT counts the divided clock output by the ø-based prescaler.
1 TCNT counts the divided clock output by the øSUB-based prescaler (PSS).
Timer enable
0 Initializes TCNT to H'00 and disables the counting operation.
1 TCNT performs counting operation.
0
Interval timer mode: Interval timer interrupt (WOVI) request
sent to CPU when overflow occurs at TCNT.
1
Watchdog timer mode: Reset or NMI interrupt request sent to
CPU when overflow occurs at TCNT.
H'FFA2 (W), H'FFA2 (R)
3
2
1
RST/NMI
CKS2
CKS1
0
0
0
R/W
R/W
R/W
Clock select 2 to 0
PSS
CSK2
0
0
1
1
0
1
Note: * The overflow cycle starts when TCNT starts counting from H'00 and ends
when an overflow occurs.
0
CKS0
0
R/W
CSK1
CSK0
Clock
20.4 µs
0
0
ø/2
652.8 µs
1
ø/64
1
0
ø/128
1.3 ms
1
ø/512
5.2 ms
0
0
ø/2048
20.9 ms
1
ø/8192
83.6 ms
1
0
ø/32768
334.2 ms
1
ø/131072
1.34 s
0
0
øSUB/2
15.6 ms
1
øSUB/4
31.3 ms
1
0
øSUB/8
62.5 ms
1
øSUB/16
125 ms
0
0
øSUB/32
250 ms
1
øSUB/64
500 ms
1
0
øSUB/128
1 s
1
øSUB/256
2 s
WDT1
Overflow cycle *
(when ø= 25MHz)
(when øSUB=32.768kHz)
1097
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