Hitachi H8S/2633 Hardware Manual page 1090

MAR1BH—Memory Address Register 1BH
MAR1BL—Memory Address Register 1BL
31
Bit :
—
MAR1BH :
Initial value : 0
—
R/W :
15
Bit :
MAR1BL :
Initial value : *
R/W
R/W :
In short address mode: Specifies transfer destination/transfer source address
In full address mode:
*: Undefined
ETCR1B—Transfer Count Register 1B
Bit
ETCR1B
Initial value
R/W
Sequential mode
and idle mode
Repeat mode
Block transfer mode
*: Undefined
Note: Not used in normal mode.
1078
30 29 28 27
— — — —
0 0 0 0
— — — —
14 13 12 11
* * * *
R/W R/W R/W R/W
:
15 14 13 12
:
:
* * * *
:
R/W R/W R/W R/W
Holds number of transfers
H'FEF8
H'FEFA
26 25 24 23
— — —
0 0 0 *
— — — R/W
10 9 8 7
* * * *
R/W R/W R/W R/W
Not used
H'FEFE
11 10 9 8
* * * *
R/W R/W R/W R/W
Transfer counter
Block transfer counter
22 21 20 19
* * * *
R/W R/W R/W R/W
6 5 4 3
* * * *
R/W R/W R/W R/W
7 6 5 4
* * * *
R/W R/W R/W R/W R/W
Transfer counter
DMAC
DMAC
18 17 16
* * *
R/W R/W R/W
2 1 0
* * *
R/W R/W R/W
DMAC
3 2 1 0
* * * *
R/W R/W R/W