Advertisement
DMABCR—DMA Band Control Register
Short address mode
Bit
:
DMABCRH
:
FAE1
Initial value
:
R/W
:
Single address enable 0
0
Transfer in dual address mode.
1
Transfer in single address mode.
Single address enable 1
0
Transfer in dual address mode.
1
Transfer in single address mode.
Full address enable 0
0
Short address mode.
1
Full address mode.
Full address enable 1
0
Short address mode.
1
Full address mode.
Bit
:
DMABCRL
:
DTE1B
Initial value
:
R/W
:
Data transfer enable 1A
Data transfer enable 1B
0
1
15
14
13
FAE0
SAE1
0
0
0
R/W
R/W
R/W
7
6
5
DTE1A
DTE0B
0
0
0
R/W
R/W
R/W
Data transfer enable 0A
0
Data transfer disabled.
1
Data transfer enabled.
Data transfer enable 0B
0
Data transfer disabled.
1
Data transfer enabled.
0
Data transfer disabled.
1
Data transfer enabled.
Data transfer disabled.
Data transfer enabled.
H'FF66
12
11
SAE0
DTA1B
0
0
R/W
R/W
Data transfer acknowledge 1B
0
Clearing of selected internal interrupt factor at DMA transfer disabled.
1
Clearing of selected internal interrupt factor at DMA transfer enabled.
Data transfer acknowledge 1A
0
Clearing of selected internal interrupt factor at DMA transfer disabled.
1
Clearing of selected internal interrupt factor at DMA transfer enabled.
Data transfer acknowledge 0B
0
Clearing of selected internal interrupt factor at DMA transfer disabled.
1
Clearing of selected internal interrupt factor at DMA transfer enabled.
Data transfer acknowledge 0A
Clearing of selected internal interrupt factor at DMA transfer disabled.
0
1
Clearing of selected internal interrupt factor at DMA transfer enabled.
4
3
DTE0A
DTIE1B
DTIE1A
0
0
R/W
R/W
Data transfer interrupt enable 1B
0
Transfer end interrupt disabled.
1
Transfer end interrupt enabled.
Data transfer interrupt enable 1A
0
Transfer end interrupt disabled.
1
Transfer end interrupt enabled.
Data transfer interrupt enable 0B
0
1
Data transfer interrupt enable 0A
0
1
10
9
8
DTA1A
DTA0B
DTA0A
0
0
0
R/W
R/W
R/W
2
1
0
DTIE0B
DTIE0A
0
0
0
R/W
R/W
R/W
Transfer end interrupt disabled.
Transfer end interrupt enabled.
Transfer end interrupt disabled.
Transfer end interrupt enabled.
DMAC
1085
Advertisement
