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DMACR0A—DMA Control Register 0A
DMACR0B—DMA Control Register 0B
DMACR1A—DMA Control Register 1A
DMACR1B—DMA Control Register 1B
Full address mode
Bit
:
DTSZ
DMACRA
:
Initial value
:
R/W
:
R/W
Data Transfer Size
0
1
1082
15
14
SAID
SAIDE
0
0
R/W
Source Address Increment/Decrement
0
0
MARA is fixed
1
MARA is incremented after a data transfer
• When DTSZ = 0, MARA is incremented by 1 after a transfer
• When DTSZ = 1, MARA is incremented by 2 after a transfer
1
0
MARA is fixed
1
MARA is decremented after a data transfer
• When DTSZ = 0, MARA is decremented by 1 after a transfer
• When DTSZ = 1, MARA is decremented by 2 after a transfer
Byte-size transfer
Word-size transfer
13
12
BLKDIR
0
0
R/W
R/W
Block Direction/Block Enable
0
0
Transfer in normal mode
1
Transfer in block transfer mode,
destination is block area
1
0
Transfer in normal mode
1
Transfer in block transfer mode,
source is block area
H'FF62
H'FF63
H'FF64
H'FF65
11
10
BLKE
—
0
0
R/W
R/W
DMAC
DMAC
DMAC
DMAC
9
8
—
—
0
0
R/W
R/W
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