Hitachi H8S/2633 Hardware Manual page 1117

P1n
*
Internal address bus
Legend
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
n = 2 or 3
Note: * Priority order: address output > output compare output/PWM output > pulse output > DR output
Figure C-1 (b) Port 1 Block Diagram (Pins P12 and P13)
Reset
R
Q D
P1nDDR
C
WDDR1
Reset
R
Q D
P1nDR
C
WDR1
RDR1
RPOR1
System controller
Address output enable
PPG module
Pulse output enable
Pulse output
TPU module
Output compare output/
PWM output enable
Output compare output/
PWM output
Input capture input
External clock input
1105