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TCNT0—Timer Counter 0
TCNT1—Timer Counter 1
Bit
:
Initial value
:
R/W
:
R/W
Note: TCNT is write-protected by a password to prevent accidental overwriting.
For details see section 15.2.5, Notes on Register Access.
RSTCSR—Reset Control/Status Register
Bit
:
WOVF
Initial value
:
R/W
:
R/(W)*
Watchdog timer overflow flag
0
[Clearing]
Writing 0 to WOVF after reading TCSR when WOVF=1.
1
[Setting]
When, in watchdog timer mode, TCNT overflows (H'FF→ H'00).
Notes: * Only 0 can be written to these bits (to clear these flags).
TCNT is write-protected by a password to prevent accidental overwriting.
For details see section 15.2.5, Notes on Register Access.
7
6
0
0
R/W
R/W
7
6
RSTE
RSTS
0
0
R/W
R/W
Reset select
0 Power-on reset.
1 Manual reset.
Reset enable
0 No internal reset on TCNT overflow.*
1 Internal reset performed on TCNT overflow.
Note: * The LSI is not internally reset, but TCNT and TCSR
in WDT are reset.
H'FF74 (W), H'FF75 (R)
H'FFA2 (W), H'FFA3 (R)
5
4
0
0
R/W
R/W
H'FF76 (W), H'FF77 (R)
5
4
—
0
1
—
3
2
0
0
R/W
R/W
3
2
—
—
1
1
—
—
WDT0
WDT1
1
0
0
0
R/W
WDT0
1
0
—
—
1
1
—
—
1089
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