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Full address mode
Bit
:
7
DMACRB
:
—
Initial value
:
0
R/W
:
R/W
Data Transfer Factor
DTF3 DTF2 DTF1 DTF0
0
0
1
1
0
1
Note: * Detected as a low level in the first transfer after transfer is enabled.
Destination Address Increment/Decrement
0
0
MARB is fixed
1
MARB is incremented after a data transfer
• When DTSZ = 0, MARB is incremented by 1 after a transfer
• When DTSZ = 1, MARB is incremented by 2 after a transfer
1
0
MARB is fixed
1
MARB is decremented after a data transfer
• When DTSZ = 0, MARB is decremented by 1 after a transfer
• When DTSZ = 1, MARB is decremented by 2 after a transfer
6
5
DAID
DAIDE
0
0
R/W
R/W
Block Transfer Mode
0
0
—
1
Activated by A/D converter
conversion end interrupt
Activated by DREQ pin falling edge
1
0
input*
Activated by DREQ pin low-level input
1
0
0
Activated by SCI channel 0
transmit-data-empty interrupt
1
Activated by SCI channel 0
reception complete interrupt
1
0
Activated by SCI channel 1
transmit-data-empty interrupt
1
Activated by SCI channel 1
reception complete interrupt
0
0
Activated by TPU channel 0 compare
match/input capture A interrupt
1
Activated by TPU channel 1 compare
match/input capture A interrupt
1
0
Activated by TPU channel 2 compare
match/input capture A interrupt
1
Activated by TPU channel 3 compare
match/input capture A interrupt
0
0
Activated by TPU channel 4 compare
match/input capture A interrupt
1
Activated by TPU channel 5 compare
match/input capture A interrupt
1
0
—
1
—
4
3
—
DTF3
DTF2
0
0
R/W
R/W
2
1
DTF1
DTF0
0
0
R/W
R/W
Normal Mode
—
—
Activated by DREQ pin
falling edge input
Activated by DREQ pin
low-level input
—
—
Auto-request (cycle steal)
Auto-request (burst)
—
—
—
—
—
—
—
—
0
0
R/W
1083
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