Hitachi H8S/2633 Hardware Manual page 1163

MCU
Port Name Operating
Pin Name Mode
PG3/CS1 4 to 6
PG2/CS2
7
PG1/CS3/ 4 to 6
OE/IRQ7
7
PG0/CAS/ 4 to 6
IRQ6
7
Legend:
H : High level
L : Low level
T : High impedance
kept : Input port becomes high-impedance, output port retains state
DDR : Data direction register
OPE : Output port enable
WAITE : Wait input enable
BRLE : Bus release enable
BREQOE : BREQO pin enable
DRAME : DRAM space setting
LCASE : DRAM space setting, CW2 = LCASS = 0
Note: * Indicates the state after completion of the executing bus cycle.
Power-
On Manual
Reset Reset
T kept
T kept
T kept
T kept
T kept
T kept
Hardware Software
Standby Standby
Mode Mode
T [DDR = 1,
OPE = 0]
T
[DDR = 1,
OPE = 1]
H
[DDR = 0]
T
T kept
T [DDR = 1,
OPE = 0]
T
[DDR = 1,
OPE = 1]
H
[DDR = 0]
T
T kept
T [DRAME = 0]
kept
[DRAME = 1,
OPE = 1]
CAS
[DRAME = 1,
OPE = 1]
T
T kept
Program
Bus Execution
Release State
State Sleep Mode
T [DDR = 0]
Input port
[DDR = 1]
CS2 to CS1
kept I/O port
T [DDR = 0]
Input port
[OE = 0,
DDR = 1]
CS3
[OE = 1,
DDR = 1]
OE
kept I/O port
T [DRAME = 0]
I/O port
[DRAME = 1]
CAS
kept I/O port
1151