M Ode-Control Register - Fujitsu MB86617A Specification Sheet

LSI S pecification

7.1. M ode-control Register

Mode-control register is the register that performs the relative setting of various operation mode of this LSI.
Bit Bit
AD R/W
15 14
00h R/W - -
Initial Value '0' '0'
BIT Bit Name
15 - 12 reserved
11 CPS soft reset
10 clk off
s-ID store
9
Note 1)
8 Cp_through
7 Sync_in
6 Sync_out
5 reserved
Iso-FIFO
4
no clr
Rev.1.0
Bit Bit Bit Bit
13 12 11 10
CPS
clk
- -
soft
off
reset
'0' '0' '0' '0'
Action Value
Read - Always indicate '0'.
Write - Always write in '0'.
PHY/LINK is reset by writing '0' after writing '1' (not automatic clear)
Read/ Note:
-
Write 1) Perform read modify write so as not to re-write other bit.
2) Write '0' after 500 ns minimum passed after writing '1'.
0 Not stop clock for providing to TSP I/F, CP I/F and data bridge.
Read/
Write
Stop clock for providing to TSP I/F, CP I/F and data bridge when PMODE input
1
terminal is in 'H'.
0 Deletes Self-ID packet in spite of receiving it during bus reset.
Read/
In case of receiving Self-ID packet during bus reset process, this bit stores 512 byte
Write
1
at maximum accompanying with both Asynchronous receive FIFO and
Asynchronous transmit FIFO.
0 Enable CP -IC interface.(Needs external CP IC)
Read/
Write
1 Disable CP -IC interface. CP-IC interface i s internally by passed.
TSSYNCA and TSSYNCB signals are neccesary to detect the first byte of the input
0
data to TSP interface.
Read/
Write
TSSYNCA and TSSYNCB signals are not neccesary to detect the first byte of the
1
input data to TSP interface.
TSSYNCA and TSSYNCB signals are not asserted when the data is outputted from
0
TSP interface.
Read/
Write
TSSYNCA and TSSYNCB signals are asserted when the data is outputted from TSP
1
interface.
Read 0 Always indicate '0'.
Write 0 Always write in '0'.
0 Clears receive Isochronous-FIFO when bus reset occurred.
Read/
Write
1 Does not clear Isochronous-FIFO when bus reset occurred.
Bit Bit Bit Bit
9 8 7 6
Cp_
s-ID
- -
trhrou
store
gh
'1' '0' '0' '0'
Function
27
MB86617A
Bit Bit Bit Bit
5 4 3 2
Iso-FI Asyn-
send/re
-
FO no FIFOs
c
clr el
'0' '1' '0' '1'
Fujitsu VLSI
Bit Bit
1 0
TSP CP
stand- stand-
by by
'1' '1'