Table of Contents
Advertisement
5.3.2
PLL and Special Configuration Control Register (PSCCR)
The PLL and Special Configuration Control Register adds the selection of a PLL clock
multiplier.
■ Configuration of the PLL and Special Configuration Control Register (PSCCR)
Figure 5.3-3 shows the configuration of the PLL and Special Configuration Control Register (PSCCR).
Table 5.3-2 describes the function of each bit of the PLL and Special Configuration Control Register
(PSCCR).
Figure 5.3-3 Configuration of the PLL and Special Configuration Control Register (PSCCR)
bit
15
14
Address:
0 0 3 5 C F
Reserved
H
Reserved Reserved Reserved
-
-
: Write only
W
X
: Undefined value
-
: Undefined
: Initial value
13
12
11
10
9
Reserved Reserved
Reserved
-
-
W
W
W
8
CS2
(PSCCR)
X X X X 0 0 0 0
W
Additional multiplier selection bit
CS2
PLL clock multiplier x1, x2, x3, x4 (depending
0
on the setting of the CS1 and CS0 bits of CKSCR)
PLL clock multiplier x2, x4, x6, x8 (depending
1
on the setting of the CS1 and CS0 bits of CKSCR)
Reserved
Always write "0" to this bit
0
The value read from this bit is always "X".
Reserved
Always write "0" to this bit
0
The value read from this bit is always "X".
Reserved
Always write "0" to this bit
0
The value read from this bit is always "X".
Reserved
Always write "0" to this bit
XXXX
The value read from these bit is always "X".
CHAPTER 5 CLOCKS
Initial value
B
Reserved bit
Reserved bit
Reserved bit
Reserved bits
95
Advertisement
Table of Contents
