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DES/3DES
8.3.3 DES/3DES INTERRUPT ENABLE REGISTER
Bit Number
[0]
Int Idle
Reserved
[3:1]
[4]
Int Available
DESINFIFO
Reserved
[7:5]
Int Valid DESOUTFIFO
[8]
8.3.4 DES/3DES RUN ENABLE REGISTER
Bit Number
[0]
Run Enable
8.3.5 DES/3DES KEY1 LEFT/RIGHT SIDE REGISTER
Bit Number
[1:32]
Key 1 Left Half
Bit Number
[33:64]
Key 1 Right Half
8-6
Table 8-4. DES/3DES Interrupt Enable Register Description
Bit Name
Interrupt enable register for DES/3DES engine operation
0 = Disable
1 = Interrupt signal is generated when the status register [0] (Idle) bit
goes to high which means the end of the current DES/3DES
operation.
Reserved
Interrupt enable register for input FIFO, DESINFIFO
0 = Disable
1 = Interrupt signal is generated when the status register [4]
(Available DESINFIFO) bit goes to high
Reserved
Interrupt enable register for output FIFO, DESOUTFIFO
0 = Disable
1 = Interrupt signal is generated when the status register [8] (Valid
DESOUTFIFO) bit goes to high
Table 8-5. DES/3DES Run Enable Register Description
Bit Name
If you set this bit to 1, DES/3DES engine begin to run. This bit is the
same register as the Run Enable bit of the DES/3DES Control
Register. You can read this bit by addressing 0x00, too.
Table 8-6. DES/3DES Key1 Left Side Register Description
Bit Name
The left half of the Key1 should be stored to this register. The 8
of each byte is parity bit, and it isn't used for encryption/decryption.
Table 8-7. DES/3DES Key 1 Right Side Register Description
Bit Name
The right half of the Key1 should be stored to this register. The 8
bit of each byte is parity bit, and it isn't used for
encryption/decryption.
Description
Description
Description
Description
S3C2501X
th
bit
th
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