Programming Guide; Initialization; Play Mode (Tx Mode) With Dma; Recording Mode (Rx Mode) With Dma - Samsung S5PC110 Manual

Risc microprocessor
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S5PC110_UM

2.7 PROGRAMMING GUIDE

The IIS bus interface can be accessed either by the processor using programmed I/O instructions or by the DMA
controller.

2.7.1 INITIALIZATION

1. Before you use IIS bus interface, you must configure GPIOs to IIS mode. Check signal's direction. I2SLRCLK,
I2SSCLK and I2SCDCLK is inout-type. The I2SSDI and I2SSDO is input and output respectively.
2. Select clock source. S5PC110 has three clock sources, namely, Audio bus clock, EPLL and external codec.
For more information, refer

2.7.2 PLAY MODE (TX MODE) WITH DMA

1. TXFIFO is flushed before operation. If you do not distinguish Master/Slave mode from TX/RX mode, you must
study Master/Slave mode and TX/RX mode. Refer Master/Slave chapter.
2. Configure I2SMOD register and I2SPSR (IIS pre-scaler register).
3. To operate system in stability, the internal TXFIFO should be almost full before transmission. To satisfy this,
start TXDMA before asserting I2SACTIVE.
4. Basically, IIS bus does not support the interrupt. Therefore, you can only check state by polling through
accessing SFR.
5. If TXFIFO is full, you can assert I2SACTIVE.

2.7.3 RECORDING MODE (RX MODE) WITH DMA

1. RXFIFO is flushed before operation. Also, if you don't distinguish between Master/Slave mode and TX/RX
mode, you must study Master/Slave mode and TX/RX mode. Refer Master/Slave chapter.
2. Configure I2SMOD register and I2SPSR (IIS pre-scaler register).
3. To operate system in stability, the internal RXFIFO should have at least one data before DMA operation. To
satisfy this, assert I2SACTIVE before starting RXDMA.
4. Check RXFIFO state by polling through accessing SFR.
5. If RXFIFO is not empty, start RXDMACTIVE.
and
Figure 2-2
Figure
2-3.
2 IIS MULTI AUDIO INTERFACE
2-12

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