Once Debug Output (Debug); Once Controller Registers; Once Command Register (Ocmr); Once Control Register (Ocr) - Motorola M-CORE MMC2001 Series Reference Manual

16.5.7 OnCE Debug Output (DEBUG)

The OnCE debug output (DEBUG) is used to indicate to on-chip resources that a
debug session is in progress. Peripherals and other units may use this signal to mod-
ify normal operation for the duration of a debug session. This may involve the CPU
executing a sequence of instructions solely for the purpose of visibility/system control.
These instructions are not part of the normal instruction stream the CPU would have
executed had it not been placed in debug mode.
This signal is asserted the first time the CPU enters the debug state and remains
asserted until the CPU is released by a write to the OnCE command register with the
GO and EX bits set, and a register specified as either "No register selected" or the
CPUSCR. This signal remains asserted even though the CPU may enter and exit the
debug state for each instruction executed under control of the OnCE controller. See
16.6.1 OnCE Command Register (OCMR) for more information on the function of
the GO and EX bits.

16.6 OnCE Controller Registers

This section describes the OnCE controller registers:

• OnCE Command Register (OCMR)

• OnCE Control Register (OCR)

• OnCE Status Register (OSR)

All OnCE registers are addressed by means of the RS field in the OMCR, as shown in
Table 16-1.
Other OnCE registers are described in 16.8 Memory Breakpoint Logic and 16.9
OnCE Trace Logic.
16.6.1 OnCE Command Register (OCMR)
The OnCE command register (OCMR) is an 8-bit shift register that receives its serial
data from the TDI pin. This register corresponds to the JTAG IR, and is loaded when
the update-IR TAP controller state is entered. It holds the 8-bit commands shifted in
during the shift-IR controller state to be used as input for the OnCE decoder. The
OCMR contains fields for controlling access to a OnCE resource, as well as control-
ling single-step operation, and exit from OnCE mode.
Although the OCMR is updated during the update-IR TAP controller state, the corre-
sponding resource is accessed in the DR scan sequence of the TAP controller, and
as such, the update-DR state must be transitioned through in order for an access to
occur. In addition, the update-DR state must also be transitioned through in order for
the single-step and/or exit functionality to be performed, even though the command
appears to have no data resource requirement associated with it.
The command register is shown in Figure 16-4.
MOTOROLA
16-6
Freescale Semiconductor, Inc.
OnCE™ DEBUG MODULE
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MMC2001
REFERENCE MANUAL