Clock Count Field Settings - Motorola M-CORE MMC2001 Series Reference Manual

PHA — Phase
This bit controls the phase shift of the SPI_CLK. (See Figure 12-2)
0 = Normal phase
1 = Shift advance to opposite phase
POL — Polarity
This bit controls the polarity of the SPI_CLK. (See Figure 12-2)
0 = Normal polarity
1 = Inverted polarity
SPIGP — SPI_GP Control
This bit controls the data on the SPI_GP pin.
0 = Pin driven low
1 = Pin driven high
BAUD RATE
These bits select the baud rate of the ISPI bit clock based on divisions of the system
clock. The master clock for the ISPI is HI_REFCLK.
CLOCK COUNT
These bits select the length of the transfer and control the justification of data. From
two to 16 bits can be transferred. A count of all zeros causes the ISPI to be disabled.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 12-2 BAUD RATE Field Settings
Value
000
001
010
011
100
101
110
111
Table 12-3 CLOCK COUNT Field Settings
Value
0000
0001
.
.
0111
.
.
1111
INTERVAL MODE SERIAL PERIPHERAL INTERFACE
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Divide By
8
16
32
64
128
256
512
1024
Meaning
Disable ISPI
2-bit transfer
.
.
8-bit transfer
.
.
16-bit transfer
MOTOROLA
12-7