Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2294

Table 31-107: EMAC_DMA2_OPMODE Register Fields (Continued)
Bit No.
(Access)
13 ST
(R/W)
7 FEF
(R/W)
6 FUF
(R/W)
5 DGF
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Start/Stop Transmission.
The EMAC_DMA2_OPMODE.ST bit, when set, places transmission in the Running
state, and the DMA checks the Transmit List at the current position for a frame to be
transmitted. Descriptor acquisition is attempted either from the current position in the
list, which is the Transmit List Base Address set by Transmit Descriptor List Address,
or from the position retained when transmission was stopped previously. If the current
descriptor is not owned by the DMA, transmission enters the Suspended state, and the
EMAC_DMA2_STAT.TU bit is set.
The Start Transmission command is effective only when transmission is stopped. If the
command is issued before setting the
then the DMA behavior is unpredictable. When this bit is reset, the transmission proc-
ess is placed in the Stopped state after completing the transmission of the current
frame. The Next Descriptor position in the Transmit List is saved, and becomes the
current position when transmission is restarted. The stop transmission command is ef-
fective only when the transmission of the current frame is complete or the transmission
is in the Suspended state.
Forward Error Frames.
The EMAC_DMA2_OPMODE.FEF bit, when reset, directs the Rx FIFO to drop
frames with error status (CRC error, collision error, giant frame, watchdog timeout,
overflow). However, if the frames start byte (write) pointer is already transferred to the
read controller side (in Threshold mode), then the frames are not dropped. When
EMAC_DMA2_OPMODE.FEF bit is set, all frames except runt error frames are for-
warded to the DMA. But when Rx FIFO overflows when a partial frame is written,
then such frames are dropped even when EMAC_DMA2_OPMODE.FEF is set.
Forward Undersized good Frames.
The EMAC_DMA2_OPMODE.FUF bit, when set, directs the Rx FIFO to forward Un-
dersized frames (frames with no Error and length less than 64 bytes) including pad-
bytes and CRC). When reset, the Rx FIFO drops all frames of less than 64 bytes, un-
less it is already transferred because of lower value of Receive Threshold (for example,
EMAC_DMA2_OPMODE.RTC =01).
Drop Giant Frames.
The EMAC_DMA2_OPMODE.DGF bit, when set, the MAC drops the received giant
frames in the Rx FIFO, that is, frames that are larger than the computed giant frame
limit. When reset, the MAC does not drop the giant frames in the Rx FIFO.
ADSP-SC58x EMAC Register Descriptions
Description/Enumeration
EMAC_DMA2_TXDSC_CUR address register,
31–203