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M16C/62P Group (M16C/62P, M16C/62PT)
21.1 Port Pi Direction Register (PDi Register, i = 0 to 13)
Figure 21.7 shows the direction registers.
This register selects whether the I/O port is to be used for input or output. The bits in this register corre-
spond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
No direction register bit for P8_5 is available.
21.2 Port Pi Register (Pi Register, i = 0 to 13)
Figure 21.8 show the Pi registers.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For
ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data
can be written to the port latch by writing to the Pi register. The data written to the port latch is output from
the pin. The bits in the Pi register correspond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
21.3 Pull-up Control Register 0 to Pull-up Control Register 3 (PUR0 to PUR3 Registers)
Figure 21.9 and 21.10 show the PUR0 to PUR3 registers.
The PUR0 to PUR2 register bits can be used to select whether or not to pull the corresponding port high in
4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is
set for input mode. To use ports P11 to P14, set the PU37 bit in the PUR3 register to "1".
However, the pull-up control register has no effect on P0 to P3, P4_0 to P4_3, and P5 during memory
extension and microprocessor modes. Although the register contents can be modified, no pull-up resistors
are connected.
21.4 Port Control Register (PCR Register)
Figure 21.11 shows the port control register.
When the P1 register is read after setting the PCR0 bit in the PCR register to "1," the corresponding port
latch can be read no matter how the PD1 register is set.
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21. Programmable I/O Ports
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