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HARDWARE
FUNCTION BLOCK OPERATIONS
Table 22 Key-on wakeup control register, pull-up control register, and interrupt control register
Key-on wakeup control register K0
Pins P1
and P1
2
K0
3
control bit
Pins P1
and P1
0
K0
2
control bit
Pins P0
and P0
2
K0
1
control bit
Pins P0
and P0
0
K0
0
control bit
Pull-up control register PU0
Pins P1
and P1
2
PU0
3
control bit
Pins P1
and P1
0
PU0
2
control bit
Pins P0
and P0
2
PU0
1
control bit
Pins P0
and P0
0
PU0
0
control bit
Interrupt control register I1
I1
Not used
3
Interrupt valid waveform for INT0 pin/
I1
2
return level selection bit (Note 2)
I1
INT0 pin edge detection circuit control bit
1
INT0 pin
I1
0
timer 1 control enable bit
Interrupt control register I2
I2
Not used
3
Interrupt valid waveform for INT1 pin/
I2
2
return level selection bit (Note 3)
I2
INT1 pin edge detection circuit control bit
1
INT1 pin
I2
0
timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: When the contents of I1
3: When the contents of I2
1-56
key-on wakeup
3
key-on wakeup
1
key-on wakeup
3
key-on wakeup
1
pull-up transistor
3
pull-up transistor
1
pull-up transistor
3
pull-up transistor
1
is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
2
is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
2
4513/4514 Group User's Manual
at reset : 0000
2
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
Key-on wakeup used
at reset : 0000
2
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
at reset : 0000
2
0
This bit has no function, but read/write is enabled.
1
Falling waveform ("L" level of INT0 pin is recognized with the SNZI0
0
instruction)/"L" level
Rising waveform ("H" level of INT0 pin is recognized with the SNZI0
1
instruction)/"H" level
0
One-sided edge detected
1
Both edges detected
0
Disabled
1
Enabled
at reset : 0000
2
0
This bit has no function, but read/write is enabled.
1
Falling waveform ("L" level of INT1 pin is recognized with the SNZI1
0
instruction)/"L" level
Rising waveform ("H" level of INT1 pin is recognized with the SNZI1
1
instruction)/"H" level
0
One-sided edge detected
1
Both edges detected
0
Disabled
1
Enabled
at RAM back-up : state retained
at RAM back-up : state retained
at RAM back-up : state retained
at RAM back-up : state retained
R/W
R/W
R/W
R/W
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