Special Mode 4 (Sim Mode) (Uart2) - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

Special Mode 4 (SIM Mode) (UART2)

Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TxD
Tables 1.15.16 lists the specifications of SIM mode. Table 1.15.17 lists the registers used in the SIM
mode and the register values set. Figure 1.15.30 shows the typical transmit/receive timing in SIM mode.
Table 1.15.16 SIM Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
(Note 2)
generation timing
Error detection
Note 1: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC
register does not change.
Note 2: A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to "1" (transmit
is completed) and U2ERE bit to "1" (error signal output) after reset. Therefore, when using SIM
mode, be sure to set the IR bit to "0" (interrupt not requested) after setting these bits.
Rev.1.00 2003.05.30 page 172
• Direct format
• Inverse format
• U2MR register's CKDIR bit = 0 (internal clock) : fi/ 16(n+1)
fi = f , f , f , f . n: Setting value of U2BRG register
1SIO 2SIO 8SIO 32SIO
• CKDIR bit = 1 (external clock) : f
f : Input from CLK pin.
EXT 2
• Before transmission can start, the following requirements must be met
_
The TE bit of U2C1 register = 1 (transmission enabled)
_
The TI bit of U2C1 register = 0 (data present in U2TB register)
• Before reception can start, the following requirements must be met
_
The RE bit of U2C1 register = 1 (reception enabled)
_
Start bit detection
• For transmission
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit = 1)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
• Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD pin.
2
During transmission, a parity error is detected by the level of input to the R
when a transmission interrupt occurs
• Error sum flag
This flag is set to "1" when any of the overrun, framing, and parity errors is encountered
pin when a parity error is detected.
2
Specification
/16(n+1)
EXT
n: Setting value of U2BRG register
Serial I/O (Special Modes)
00 to FF
16 16
00 to FF
16 16
D pin
X 2