Renesas M16C/60 Series Hardware Manual page 167

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M16C/6N5 Group
• Example of receive timing when transfer data is 8-bit long (parity disabled, one stop bit)
UiBRG count
source
"1"
UiC1 register
RE bit
"0"
RxD
i
Transfer clock
"1"
UiC1 register
RI bit
"0"
"H"
RTS
i
"L"
"1"
SiRIC register
IR bit
"0"
i = 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
UiMR register PRYE bit = 0 (parity disabled)
UiMR register STPS bit = 0 (1 stop bit)
UiC0 register CRD bit = 0 (CTS
Figure 1.15.16 Receive Operation
(a) LSB First/MSB First Select Function
As shown in Figure 1.15.17, use the UiC0 register's UFORM bit to select the transfer format. This
function is valid when transfer data is 8-bit long.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLK i
T D
X i
R D
X i
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLK
i
T D
X i
R D
X i
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
Note: This applies to the case where the UiC0 register's CKPOL bit = 0 (transmit data output
Figure 1.15.17 Transfer Format
Rev.1.00 2003.05.30 page 153
Start bit
Sampled "L"
Reception triggered when transfer clock
is generated by falling edge of start bit
Set to "0" when interrupt request is accepted, or set to "0" in a program.
/RTS enabled), CRS bit = 1 (RTS
i i
ST D0 D
1
ST D D
0 1
D
ST D 6
7
ST D D
7 6
at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the UiC1 register's UiLCH bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit)
and UiMR register's PRYE bit = 1 (parity enabled).
D
D
1
0
Receive data taken in
Transferred from UARTi receive
register to UiRB register
selected)
i
D D D D D
2 3 4 5 6
D D D D D
2 3 4 5 6
D D D D D
5 4 3 2 1
D D D D D
5 4 3 2 1
Serial I/O (UART Mode)
Stop bit
D
7
D P SP
7
D P SP
7
D
0 P SP
D
0 P SP