Renesas M16C/60 Series Hardware Manual page 240

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M16C/6N5 Group
Transmission
Figure 1.19.27 shows the timing of the transmit sequence.
TrmReq bit
TrmActive bit
SentData bit
CAN0 Successful
Transmission Interrupt
TrmState bit
TrmSucc bit
MBOX bit
j = 0 to 15
Figure 1.19.27 Timing of Transmit Sequence
1) If one or more of the slots of a module has a request for transmission, the module attempts to start the
transmission at the next possible time (depending on the bus condition).
2) The TrmActive bit in the C0MCTLj register ( j = 0 to 15) of the lowest slot with transmit request is set to
"1" (transmitting). Also the TrmState bit in the C0STR register is set to "1" (transmitter). If the arbitration
is lost against another CAN node both bits are set to "0" (idle) again (A).
3a) When the arbitration was won, but the transmission was not successful;
The module will attempt to re-transmit.
3b) When the arbitration was won and the transmission has been successful;
The SentData bit in the C0MCTLj register is set to "1" (transmission is successfully completed) and
TrmSucc bit in the C0STR register is set to "1" (transmitted a message successfully). If the according
interrupt enable bit in the C0ICR register is "1", the successful transmission interrupt request is occurred.
The number of the slot that was transmitted can be found in MBOX bit in the C0STR register.
4) After a successful transmission, the module will not attempt to send the slot again until it is reactivated.
To reactivate a slot for transmission, first the TrmReq bit in the C0MCTLj register has to be set to "0"
(not transmission slot). Then the Sent Data bit in the C0MCTLj register can be set to "0" (transmission
is not started or completed yet) and the TrmReq bit is can be set to "1" (transmission slot) again (B).
Note that the SentData bit is locked and cannot be set to "0" as long as TrmReq bit =1.
Rev.1.00 2003.05.30 page 226
SOF
CTx
(1)
(2)
A
(2)
(2)
A
(2)
SOF
ACK EOF IF
(4)
B
(3b)
(3b)
(3b)
(3b)
Transmission slot No.
CAN Module