Renesas M16C/60 Series Hardware Manual page 291

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
Full Status Check
When an error occurs, the FMR0 register's FMR06 or FMR07 bits are set to "1", indicating occurrence
of each specific error. Therefore, execution results can be verified by checking these status bits (full
status check). Table 1.22.6 lists errors and FMR0 register status. Figure 1.22.12 shows a full status
check flowchart and the action to be taken when each error occurs.
Table 1.22.6 Errors and FMR0 Register Status
FRM00 register
(status register)
status
FMR07 FMR06
(SR5) (SR4)
1 1
1 0
0 1
Note 1: Writing "xxFF
mode, and the command code written in the first bus cycle is nullified.
Note 2: When the FMR02 bit of FMR0 register = 1 (lock bit disabled), no error will occur under this condition.
Rev.1.00 2003.05.30 page 277
Error
Command •When any command is not written correctly
sequence error •When invalid data was written other than those that can be written
in the second bus cycle of the Lock Bit Program, Block Erase, or
Erase All Unlocked Block command (i.e., other than "xxD0
"xxFF
Erase error •When the Block Erase command was executed on locked blocks
(Note 2)
•When the Block Erase or Erase All Unlocked Block command
was executed on unlocked blocks but the blocks were not
automatically erased correctly
Program error •When the Block Erase command was executed on locked blocks
(Note 2)
•When the Program command was executed on unlocked blocks
but the blocks were not automatically programmed correctly.
•When the Lock Bit Program command was executed but not
programmed correctly
" in the second bus cycle of these commands places the microcomputer in read array
16
Error occurrence condition
") (Note 1)
16
Flash Memory
" or
16