Renesas M16C/60 Series Hardware Manual page 149

Under development
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M16C/6N5 Group
RxD data
RxDi
reverse circuit
1SP
STPS= 0
SP
2SP
STPS= 1
2SP
SP SP
1SP
i=0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: UiMR register's bits
UiERE: UiC1 register's bit
Figure 1.15.2 UARTi Transmit/Receive Unit
Rev.1.00 2003.05.30 page 135
No reverse
IOPOL=0
Reverse
IOPOL=1
PAR
disabled
Clock
synchronous
type
PRYE=0
SP PAR
PRYE=1
UART
PAR
enabled
0 0 0 0 0 0
UART
(9 bits)
PAR
UART
enabled PRYE=1
STPS= 1
PAR
STPS
PRYE=0
= 0
Clock
PAR
synchronous
disabled
type
"0"
Clock
synchronous type
UART
(7 bits)
UART
UART(7 bits)
(8 bits)
Clock
UART
synchronous type
(9 bits)
UART
(8 bits)
UART
(9 bits)
0
D D D D D
8 7 6 5
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D D D D
D
7 6 5
8
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART
(7 bits)
UART(7 bits)
UART
(8 bits)
Clock
synchronous type
Error signal output
disable
UiERE=0
Error signal
output circuit
UiERE=1
Error signal output
enable
UARTi receive register
D D D D
UiRB register
4 3 2 1 0
D D D D UiTB register
4 3 2 1 0
UARTi transmit register
No reverse
IOPOL=0
TxD data
reverse circuit
IOPOL=1
Reverse
Serial I/O
TxD
i