Renesas M16C/60 Series Hardware Manual page 42

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2
0 0 0 0
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: For the mask ROM version, this bit must be set to "0".
For the flash memory version, the PM10 bit also controls block A by enabling or disabling it.
However, the PM10 bit is automatically set to "1" when the FMR01 bit in the FMR0 register is "1" (CPU
rewrite mode).
Note 3: Effective when the PM01 to PM00 bits are set to "01
mode).
Note 4: The PM12 bit is set to "1" by writing a "1" in a program. (Writing a "0" has no effect.)
Note 5: No device model of the M16C/6N5 group has the internal ROM of 192 Kbytes or more. Accordingly, this bit
must set to "0".
The PM13 bit is automatically set to "1" when the FMR01 bit in the FMR0 register is "1" (CPU rewrite mode).
Note 6: When the PM17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal RAM,
internal ROM, or an external area.
If the CSiW bit (i = 0 to 3) in the CSR register is "0" (with wait state), the CS
one or more wait states regardless of whether the PM17 bit is set or not.
Where the RDY signal is used or multiplexed bus is used, set the CSiW bit to "0" (with wait state).
Figure 1.6.2 PM1 Register
Rev.1.00 2003.05.30 page 28
b1 b0
Symbol
PM1
Bit symbol
CS area switch bit
2
PM10 (data block enable bit)
Port P3
PM11
select bit
Watchdog timer function
PM12
select bit
Internal reserved area
PM13
expansion bit
-
Reserved bit
(b6-b4)
Wait bit
PM17
Address
0005 0XXX1000
16
Bit name
0 : 08000
1 : 10000
(Note 2)
0 : Address output
to P3 function
7 4
1 : Port function
(Note 3)
0 : Watchdog timer interrupt
1 : Watchdog timer reset (Note 4)
Internal ROM area is:
0 : 192 Kbytes or smaller
(Note 5)
1 : Expanded over 192 Kbytes
Set to "0".
0 : No wait state
(Note 6)
1 : With wait state (1 wait)
" (memory expansion mode) or "11
2
Processor Mode
After reset
2
Function
(block A disable)
to 26FFF
16 16
(block A enable)
to 26FFF
16 16
" (microprocessor
2
area is always accessed with
i
RW
RW
RW
RW
RW
RW
RW