Renesas M16C/60 Series Hardware Manual page 193

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
Table 1.15.18 SI/O3 Specifications
Item
Transfer data format
Transfer clock
Transmission/reception
start condition
Interrupt request
generation timing
CLK pin function
3
S pin function
OUT3
SIN3 pin function
Select function
Note 1: To set the S3C register's SM36 bit to "0" (external clock), follow the procedure described below.
• If the S3C register's SM34 bit = 0, write transmit data to the S3TRR register while input on the CLK
The same applies when rewriting the S3C register's SM37 bit.
• If the SM34 bit = 1, write transmit data to the S3TRR register while input on the CLK
applies when rewriting the SM37 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/O3 circuit, stop the transfer
clock after supplying eight pulses. If the SM36 bit = 1 (internal clock), the transfer clock automatically stops.
Note 2: Unlike UART0 to UART2, SI/O3 is not separated between the transfer register and buffer. Therefore, do not write
the next transmit data to the S3TRR register during transmission.
Note 3: When the S3C register's SM36 bit = 1 (internal clock), S
after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is written
to the S3TRR register during this period, S
time thereby reduced.
Note 4: When the S3C register's SM36 bit = 1 (internal clock), the transfer clock stops in the high state if the SM34 bit =
0, or stops in the low state if the SM34 bit = 1.
Rev.1.00 2003.05.30 page 179
• Transfer data length: 8 bits
• S3C register's SM36 bit = 1 (internal clock) : fj/ 2(n+1)
fj = f , f , f . n = Setting value of S3BRG register
1SIO 8SIO 32SIO
• SM36 bit = 0 (external clock) : Input from CLK
• Before transmission/reception can start, the following requirements must be met
Write transmit data to the S3TRR register (Notes 2, 3)
• When S3C register's SM34 bit = 0
The rising edge of the last transfer clock pulse (Note 4)
• When SM34 = 1
The falling edge of the last transfer clock pulse (Note 4)
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
• LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Function for setting an S
OUT3
When the S3C register's SM36 bit = 0 (external clock), the S
while not transmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
immediately goes to a high-impedance state, with the data hold
OUT3
Specification
pin (Note 1)
3
initial value set function
retains the last data for a 1/2 transfer clock period
OUT3
SI/O3
00 to FF .
16 16
pin output level
OUT3
pin is high.
3
pin is low. The same
3