Renesas M16C/60 Series Hardware Manual page 185

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M16C/6N5 Group
(1) UiSMR register ABSCS bit (bus collision detect sampling clock select)
Transfer clock
TxD
i
RxD
i
Timer Aj
(2) UiSMR register ACSE bit (auto clear of transmit enable bit)
Transfer clock
TxD
i
RxD
i
UiBCNIC register
IR bit
UiC1 register
TE bit
(3) UiSMR register SSS bit (transmit start condition select)
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
TxD
i
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxD
CLK
i
TxD
i
RxD
i
Note 1: The falling edge of RxDi when IOPOL = 0; the rising edge of RxDi when IOPOL = 1.
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxD
i = 0 to 2
This diagram applies to the case where IOPOL =1 (reversed)
Figure 1.15.29 Bus Collision Detect Function-Related Bits
Rev.1.00 2003.05.30 page 171
If ABSCS = 0, bus collision is determined at the rising edge of the transfer clock
ST D0 D1
Input to TAj
IN
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
ST D0 D1
ST D0 D1
ST D0 D1
(Note 2)
D2 D3 D4 D5 D6
If ABSCS = 1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
D2 D3 D4 D5 D6
D2 D3 D4 D5
i
D2 D3 D4 D5
.
i
Serial I/O (Special Modes)
D7 D8 SP
D7 D8 SP
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is set to "0"
(transmission disabled) when
the UiBCNIC register's IR bit = 1
(unmatching detected).
D6 D7 D8 SP
D6 D7 D8 SP