Ring Oscillator Clock; Pll Clock - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

(3) Ring Oscillator Clock

This clock, approximately 1 MHz, is supplied by a ring oscillator. This clock is used as the clock source for
the CPU and peripheral function clocks. In addition, if the PM22 bit of PM2 register is "1" (ring oscillator
clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer
(refer to "Watchdog Timer • Count source protective mode").
After reset, the ring oscillator is turned off. It is turned on by setting the CM21 bit of CM2 register to "1"
(ring oscillator clock), and is used as the clock source for the CPU and peripheral function clocks, in place
of the main clock. If the main clock stops oscillating when the CM20 bit of CM2 register is "1" (oscillation
stop, re-oscillation detection function enabled) and the CM27 bit is "1" (oscillation stop, re-oscillation
detection interrupt), the ring oscillator automatically starts operating, supplying the necessary clock for the
microcomputer.

(4) PLL Clock

The PLL clock is generated by a PLL frequency synthesizer. This clock is used as the clock source for the
CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthe-
sizer is activated by setting the PLC07 bit to "1" (PLL operation). When the PLL clock is used as the clock
source for the CPU clock, wait a fixed period of t
CM11 bit in the CM1 register to "1".
Before entering wait mode or stop mode, be sure to set the CM11 bit to "0" (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to "0"
(PLL stops). Figure 1.8.11 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
Figure 1.8.11 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency = f(X
The PLC02 to PLC00 bits can be set only once after reset. Table 1.8.2 shows the example for setting PLL
clock frequencies.
Rev.1.00 2003.05.30 page 52
(PLL) for the PLL clock to be stable, and then set the
su
) ✕ (multiplying factor set by the PLC02 to PLC00 bits of the PLC0 register)
IN
(However, PLL clock frequency = 20 MHz)
Table 1.8.2 Example for Setting PLL Clock Frequencies
Note: PLL clock frequency = 20 MHz
X
IN
PLC02 PLC01 PLC00
(MHz)
10 0 0
5 0 1
Clock Generation Circuit
Multiply PLL clock
factor
(MHz) (Note)
1 2
20
0 4