Renesas M16C/60 Series Hardware Manual page 174

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay)
1st bit
SCLi
D
SDAi
(2) IICM2 = 0, CKPH = 1 (clock delay)
1st bit
SCLi
D
SDAi
(3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0
1st bit
SCLi
D
SDAi
(4) IICM2 = 1, CKPH = 1
1st bit
SCLi
D
SDAi
i = 0 to 2
This diagram applies to the case where the following condition is met.
UiMR register CKDIR bit = 0 (slave selected)
Figure 1.15.22 Transfer to UiRB Register and Interrupt Timing
Rev.1.00 2003.05.30 page 160
2nd bit 3rd bit 4th bit 5th bit
D D D D
7
6 5 4
2nd bit 3rd bit 4th bit 5th bit
D D D D
7
6 5 4
2nd bit 3rd bit 4th bit 5th bit
D D D D
7 6 5 4
2nd bit 3rd bit 4th bit 5th bit
D D D D
7
6 5 4
b15 b9
6th bit 7th bit 8th bit 9th bit
D D D D
3 2 1 0 8
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
6th bit 7th bit 8th bit 9th bit
D
D D D
3 2 1 0 8
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
6th bit 7th bit 8th bit 9th bit
D D D D
3 2 1 0
8
Receive interrupt
Transmit interrupt
(DMA1 request)
Transfer to UiRB register
b15
6th bit 7th bit 8th bit 9th bit
D D D D
3 2 1 0 8
Receive interrupt
(DMA1 request)
Transfer to UiRB register
b8 b7 b0 b15
D D D D D D D D
0 7 6 5 4 3 2 1
UiRB register
Serial I/O (Special Modes)
(ACK, NACK)
b9 b8 b7
D D D D D D D D
8 7 6 5 4 3 2 1
UiRB register
(ACK, NACK)
b9 b8 b7
D D D D D D D D
8 7 6 5 4 3 2 1
UiRB register
(ACK, NACK)
b9 b8 b7
D D D D D D D
0 7 6 5 4 3 2
UiRB register
(ACK, NACK)
Transmit interrupt
Transfer to UiRB register
b9 b8 b7
D D D D D D D D
8 7 6 5 4 3 2 1
UiRB register
b0
D
0
b0
D
0
b0
D
1
b0
D
0