Renesas M16C/60 Series Hardware Manual page 107

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M16C/6N5 Group
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
CPU use
bus
RD signal
WR signal
Data
CPU use
bus
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
CPU use
bus
RD signal
WR signal
Data
CPU use
bus
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
CPU use
bus
RD signal
WR signal
Data
CPU use
bus
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
CPU use
bus
RD signal
WR signal
Data
CPU use
bus
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.12.5 Transfer Cycles for Source Read
Rev.1.00 2003.05.30 page 93
Source Destination
Source Destination
Source Source + 1 Destination
Source Source + 1
Source
Destination
Source Destination
Source Source + 1
Source
Dummy
CPU use
cycle
Dummy
CPU use
cycle
Dummy
CPU use
cycle
Dummy
Destination CPU use
cycle
Dummy
CPU use
cycle
Dummy
CPU use
cycle
Destination
Source + 1 Destination
DMAC
Dummy
CPU use
cycle
Dummy
CPU use
cycle