Renesas M16C/60 Series Hardware Manual page 182

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
• Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3
register's CKPH bit and the UiC0 register's CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and salves to be commu-
nicated.
(a) Master (Internal Clock)
Figure 1.15.26 shows the transmission and reception timing in master (internal clock).
Clock output
(CKPOL=0, CKPH=0)
Clock output
(CKPOL=1, CKPH=0)
Clock output
(CKPOL=0, CKPH=1)
Clock output
(CKPOL=1, CKPH=1)
Data output timing
Data input timing
Figure 1.15.26 Transmission and Reception Timing in Master Mode (Internal Clock)
(b) Slave (External Clock)
Figure 1.15.27 shows the transmission and reception timing (CKPH = 0) in slave (external clock).
Figure 1.15.28 shows the transmission and reception timing (CKPH = 1) in slave (external clock).
Rev.1.00 2003.05.30 page 168
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
D D D
0 1 2
"L"
Serial I/O (Special Modes)
D D D D
3 4 5 6
D
7